Automatic multi-stage fabric generation for FPGAs

ABSTRACT

Systems and methods to automatically or manually generate various multi-stage pyramid network based fabrics, either partially connected or fully connected, are disclosed by changing different parameters of multi-stage pyramid network including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers in any switch, connections between stages of rings either between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is Continuation Application to and claims priority of U.S. application Ser. No. 16/671,193 entitled “AUTOMATIC MULTI-STAGE FABRIC GENERATION FOR FPGAs” by Venkat Konda assigned to the same assignee as the current application, filed Nov. 1, 2019, which is Continuation Application to and claims priority of U.S. application Ser. No. 15/859,726 entitled “AUTOMATIC MULTI-STAGE FABRIC GENERATION FOR FPGAs” by Venkat Konda assigned to the same assignee as the current application, filed Jan. 1, 2018, which is Continuation In Part Application to and claims priority of U.S. application Ser. No. 14/329,876 entitled “FAST SCHEDULING AND OPTIMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Jul. 11, 2014, issued as U.S. Pat. No. 9,509,634 on Nov. 29, 2016, which claims priority of U.S. Provisional Patent Application Ser. No. 61/846,083 entitled “FAST SCHEDULING AND OPTIMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Jul. 15, 2013, which is Continuation In Part Application to and claims priority of the U.S. application Ser. No. 14/199,168 entitled “OPTIMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS FOR PRACTICAL ROUTING APPLICATIONS” by Venkat Konda assigned to the same assignee as the current application, filed Mar. 6, 2014, issued as U.S. Pat. No. 9,374,322 on Jun. 21, 201, which is a bypass continuation application and claims priority of PCT Application Serial No. PCT/US12/53814 entitled “OPTIMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS FOR PRACTICAL ROUTING APPLICATIONS” by Venkat Konda assigned to the same assignee as the current application, filed Sep. 6, 2012, which is Continuation in Part application to and claims priority to U.S. Provisional Patent Application Ser. No. 61/531,615 entitled “OPTIMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS FOR PRACTICAL ROUTING APPLICATIONS” by Venkat Konda assigned to the same assignee as the current application, filed Sep. 7, 2011.

This application is related to and incorporates by reference in its entirety the U.S. Pat. No. 8,270,400 entitled “FULLY CONNECTED GENERALIZED MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, issued Sep. 18, 2012, the U.S. Provisional Patent Application Ser. No. 60/905,526 entitled “LARGE SCALE CROSSPOINT REDUCTION WITH NONBLOCKING UNICAST & MULTICAST IN ARBITRARILY LARGE MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Mar. 6, 2007, and the U.S. Provisional Patent Application Ser. No. 60/940,383 entitled “FULLY CONNECTED GENERALIZED MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007.

This application is related to and incorporates by reference in its entirety the U.S. Pat. No. 8,170,040 entitled “FULLY CONNECTED GENERALIZED BUTTERFLY FAT TREE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, issued May 1, 2012, the U.S. Provisional Patent Application Ser. No. 60/940,387 entitled “FULLY CONNECTED GENERALIZED BUTTERFLY FAT TREE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007, and the U.S. Provisional Patent Application Ser. No. 60/940,390 entitled “FULLY CONNECTED GENERALIZED MULTI-LINK BUTTERFLY FAT TREE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007

This application is related to and incorporates by reference in its entirety the U.S. Pat. No. 8,363,649 entitled “FULLY CONNECTED GENERALIZED MULTI-LINK MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, issued Jan. 29, 2013, the U.S. Provisional Patent Application Ser. No. 60/940,389 entitled “FULLY CONNECTED GENERALIZED REARRANGEABLY NONBLOCKING MULTI-LINK MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007, the U.S. Provisional Patent Application Ser. No. 60/940,391 entitled “FULLY CONNECTED GENERALIZED FOLDED MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007 and the U.S. Provisional Patent Application Ser. No. 60/940,392 entitled “FULLY CONNECTED GENERALIZED STRICTLY NONBLOCKING MULTI-LINK MULTI-STAGE NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007.

This application is related to and incorporates by reference in its entirety the U.S. Pat. No. 8,269,523 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS” by Venkat Konda assigned to the same assignee as the current application, issued Sep. 18, 2012, the PCT Application Serial No. PCT/U08/64605 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 22, 2008, and the U.S. Provisional Patent Application Ser. No. 60/940,394 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007.

This application is related to and incorporates by reference in its entirety the U.S. Pat. No. 8,898,611 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID NETWORKS WITH LOCALITY EXPLOITATION” by Venkat Konda assigned to the same assignee as the current application, issued Nov. 25, 2014, the PCT Application Serial No. PCT/US10/52984 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID NETWORKS WITH LOCALITY EXPLOITATION” by Venkat Konda assigned to the same assignee as the current application, filed Oct. 16, 2010, the U.S. Provisional Patent Application Ser. No. 61/252,603 entitled “VLSI LAYOUTS OF FULLY CONNECTED NETWORKS WITH LOCALITY EXPLOITATION” by Venkat Konda assigned to the same assignee as the current application, filed Oct. 16, 2009, and the U.S. Provisional Patent Application Ser. No. 61/252,609 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID NETWORKS” by Venkat Konda assigned to the same assignee as the current application, filed Oct. 16, 2009.

BACKGROUND OF INVENTION

Multi-stage interconnection networks such as Benes networks and butterfly fat tree networks are widely useful in telecommunications, parallel and distributed computing. However VLSI layouts, known in the prior art, of these interconnection networks in an integrated circuit are inefficient, not scalable and not replicable.

Other multi-stage interconnection networks including butterfly fat tree networks, Banyan networks, Batcher-Banyan networks, Baseline networks, Delta networks, Omega networks and Flip networks have been widely studied particularly for self-routing packet switching applications. Also Benes Networks with radix of two have been widely studied and it is known that Benes Networks of radix two are shown to be built with back to back baseline networks which are rearrangeably nonblocking for unicast connections.

The most commonly used VLSI layout in an integrated circuit is based on a two-dimensional grid model comprising only horizontal and vertical tracks. An intuitive interconnection network that utilizes two-dimensional grid model is 2D Mesh Network and its variations such as segmented mesh networks. Hence routing networks used in VLSI layouts are typically 2D mesh networks and its variations. However Mesh Networks require large scale cross points typically with a growth rate of O(N²) where N is the number of computing elements, ports, or logic elements depending on the application.

Multi-stage interconnection network with a growth rate of O(N×log N) requires significantly small number of cross points. U.S. Pat. No. 6,185,220 entitled “Grid Layouts of Switching and Sorting Networks” granted to Muthukrishnan et al. describes a VLSI layout using existing VLSI grid model for Benes and Butterfly networks. U.S. Pat. No. 6,940,308 entitled “Interconnection Network for a Field Programmable Gate Array” granted to Wong describes a VLSI layout where switches belonging to lower stage of Benes Network are laid out close to the logic cells and switches belonging to higher stages are laid out towards the center of the layout. Pyramid networks comprise both mesh connections and tree or hierarchical connections, where mesh connections are defined as connections between same level stages or same numbered stages and hierarchical or tree connections are defined as connections between two successive or different level stages. Prior art teaches isomorphic transformations between any two stages of multi-stage networks and pyramid networks as well as between the first stage and the coupled computational blocks to the network.

Due to the inefficient and in some cases impractical VLSI layout of Benes, Benes Pyramid, Butterfly fat tree networks, and Butterfly fat pyramid networks on a semiconductor chip, today mesh networks and segmented mesh networks are widely used in the practical applications such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), and parallel computing interconnects. The prior art VLSI layouts of Benes, Benes Pyramid, Butterfly fat tree networks, Pyramid networks and VLSI layouts of mesh networks and segmented mesh networks require large area to implement the switches on the chip, large number of wires, longer wires, with increased power consumption, increased latency of the signals which effect the maximum clock speed of operation. Some networks may not even be implemented practically on a chip due to the lack of efficient layouts.

Fully connected Benes, Benes Pyramid, Butterfly fat tree networks and Butterfly fat pyramid networks are an over kill for certain practical routing applications and need to be optimized to significantly improve area, power and performance of the routing network.

SUMMARY OF INVENTION

Systems and methods to automatically generate various multi-stage pyramid network based fabrics, applicable to including Field programmable gate arrays, are disclosed. Significantly optimized multi-stage pyramid networks either partially connected or fully connected, useful in wide target applications, with VLSI layouts (or floor plans) substantially using horizontal and vertical links to route signals between inlet and outlet links of large scale sub-integrated circuit blocks and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks, (for example in an FPGA where the sub-integrated circuit blocks are Lookup Tables, or memory blocks, or DSP blocks) are disclosed. The optimized multi-stage networks in each block employ a plurality of slices of rings of stages of switches with different size multiplexer having inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side, or from right-hand side, or from both left-hand side and right-hand side, or through an incoming and outgoing links of a stage. The VLSI layouts exhibit spatial locality so that sub-integrated circuit blocks that are spatially nearer are connected with shorter hop wires.

Fabrics are generated iteratively either manually or automatically by changing different parameters including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers of a switch, connections between stages of rings which may be between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of all iterations, to route a given set of benchmarks or designs having a specific connection requirements.

Fabric disclosed provide high routability for broadcast, unicast and multicast connections, yet with the benefits of significantly lower cross points hence smaller area, lower signal latency, lower power and with significant fast scheduling or routing time. Various scheduling methods are also disclosed to schedule a set of multicast connections in the multi-stage pyramid network.

The optimized multi-stage networks V_(Comb)(N₁,N₂,d,s) & V_(D-Comb)(N₁,N₂,d,s) according to the current invention inherit the properties of one or more, in addition to additional properties, generalized multi-stage pyramid networks V(N₁,N₂,d,s) & V_(P)(N₁,N₂,d,s), generalized folded multi-stage pyramid networks V_(fold)(N₁,N₂,d,s) & V_(fold-p)(N₁,N₂,d,s), generalized butterfly fat tree and butterfly fat pyramid networks V_(bft)(N₁,N₂,d,s) & V_(bfp)(N₁,N₂,d,s), generalized multi-link multi-stage pyramid networks V_(mlink)(N₁,N₂,d,s) & V_(mlink-p)(N₁,N₂,d,s), generalized folded multi-link multi-stage pyramid networks V_(fold-mlink)(N₁,N₂,d,s) & V_(fold-mlink-p)(N₁,N₂,d,s), generalized multi-link butterfly fat tree and butterfly fat pyramid networks V_(mlink-bft)(N₁,N₂,d,s) & V_(mlink-bfp)(N₁,N₂,d,s), generalized hypercube networks V_(hcube)(N₁,N₂,d,s), and generalized cube connected cycles networks V_(CCC)(N₁,N₂,d,s) for s=1, 2, 3 or a whole number in general and d is a whole number and need not be the same in different switches or multiplexers of a ring.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a diagram 100A of an exemplary partial multi-stage pyramid network corresponding to one block with 4 inputs and 2 outputs of a computational block (hereinafter alternatively referred to as “programmable logic block”) connecting only from left-hand side, to route practical applications such as FPGA routing of hardware designs in accordance with the invention.

FIG. 1B is a diagram 100B of an exemplary partial multi-stage pyramid network corresponding to one block with 8 inputs and 4 outputs of a computational block connecting from both left-hand side and right-hand side, to route practical applications such as FPGA routing of hardware designs in accordance with the invention.

FIG. 1C is a diagram 100C of an exemplary partial multi-stage pyramid network corresponding to one block, by dividing the network into two parallel and independent slices, with 16 inputs and 4 outputs of a computational block connecting from both left-hand side and right-hand side, to route practical applications such as FPGA routing of hardware designs in accordance with the invention.

FIG. 1C1 is a diagram 100C1, FIG. 1C2 is a diagram 100C2, FIG. 1C3 is a diagram 100C3, and FIG. 1C4 is a diagram 100C4 illustrate the specific details of the diagram 100C of FIG. 1C, particularly the connections between different slices.

FIG. 1C5 is a diagram 100C5 illustrate the specific details of the diagram 100C of FIG. 1C, particularly the internal connections between two successive stages of a ring of a slice, in one embodiment.

FIG. 1C6 is a diagram 100C6 illustrate the specific details of the diagram 100C of FIG. 1C, particularly the internal connections between two successive stages of a ring of a slice, in one embodiment.

FIG. 1D is a diagram 100D of an exemplary partial multi-stage pyramid network corresponding to one slice of a block to route practical applications such as FPGA routing of hardware designs in accordance with the invention.

FIG. 2A is a diagram 200A, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2B is a diagram 200B, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2C is a diagram 200C, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2D is a diagram 200D, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2E is a diagram 200E, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2F is a diagram 200F, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2G is a diagram 200G, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2H is a diagram 200H, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2I is a diagram 200I, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2J is a diagram 200J, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2K is a diagram 200K, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2L is a diagram 200L, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2M is a diagram 200M, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 2N is a diagram 200N, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block.

FIG. 3A is a diagram 300A, in an embodiment of, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 3B is a diagram 300B, in an embodiment of, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 3C is a diagram 300C, in an embodiment of, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 3D is a diagram 300D, in an embodiment of, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 3E is a diagram 300E, in an embodiment of, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 4A is a diagram 400A, in an embodiment of, all the connections between two stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 4B is a diagram 400B, in an embodiment of, all the connections between two stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 4C is a diagram 400C, in an embodiment of, all the connections between two stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 4D is a diagram 400D, in an embodiment of, all the connections between two stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 5A is a diagram 500A, in an embodiment of, all the connections with multi-drop hop wires, between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network.

FIG. 6A is a diagram 600A, in an embodiment of, all the connections with multi-drop hop wires, between stages of multiple different rings in the same block or in multiple different blocks of a multi-stage pyramid network.

FIG. 6B is a diagram 600B, in an embodiment of, all the connections with multi-drop hop wires, between stages of multiple different rings in the same block or in multiple different blocks of a multi-stage pyramid network.

FIG. 7A is a diagram 700A, is an embodiment of hop wire connection chart corresponding to a block of multi-stage pyramid network, where the inter-ring connections are given between two successive stages of two different rings as described in diagrams 300A of FIG. 3A to 300E of FIG. 3E.

FIG. 8 is a diagram 800, is an embodiment of 2D-grid of blocks with each block corresponding to a partial multi-stage network to implement an exemplary multi-stage pyramid network, in accordance with the invention.

FIG. 9A is a diagram 900A, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 9B is a diagram 900B, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 9C is a diagram 900C, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 9D is a diagram 900D, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 9E is a diagram 900E, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 10A is a diagram 1000A, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 10B is a diagram 1000B, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 10C is a diagram 1000C, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 10D is a diagram 1000D, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 10E is a diagram 1000E, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 10F is a diagram 1000F, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 11A is a diagram 1100A, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 11B is a diagram 1100B, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 11C is a diagram 1100C, in an embodiment of, a stage in a ring of multi-stage pyramid network corresponding to one block, with delay optimizations.

FIG. 12 is a diagram 1200, in an embodiment, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network with delay optimizations.

FIG. 13 is a diagram 1300, in one embodiment, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network with delay optimizations.

FIG. 14 is a diagram 1400, in an embodiment of, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network with delay optimizations.

FIG. 15 is a diagram 1500, in an embodiment of, all the connections between two successive stages of two different rings in the same block or in two different blocks of a multi-stage pyramid network with delay optimizations.

FIG. 16A1 is a diagram 1600A1 of an exemplary prior art implementation of a two by two switch; FIG. 16A2 is a diagram 1600A2 for programmable integrated circuit prior art implementation of the diagram 1600A1 of FIG. 16A1; FIG. 16A3 is a diagram 1600A3 for one-time programmable integrated circuit prior art implementation of the diagram 1600A1 of FIG. 16A1; FIG. 16A4 is a diagram 1600A4 for integrated circuit placement and route implementation of the diagram 1600A1 of FIG. 16A1.

FIG. 17 is high-level flowchart of a scheduling method 1700 according to the invention, used to set up a set of multicast connections in the complete multi-stage pyramid network as disclosed in the current invention.

FIG. 18 is high-level flowchart of a scheduling method 1800 according to the invention, used to set up a set of multicast connections first on the external wires and then on internal wires in the complete multi-stage pyramid network as disclosed in the current invention.

FIG. 19 is high-level flowchart method or system 1900 of an automatic multi-stage pyramid network based network or fabric for an integrated circuit device including an FGPA according to the invention, used to iteratively generate an optimal network or fabric to meet a required criteria while successfully routing a set of benchmarks using the scheduling methods 1700 or 1800 in some embodiments as disclosed in the current invention.

DETAILED DESCRIPTION OF THE INVENTION

Fully connected multi-stage pyramid networks are an over kill in every dimension such as area, power, and performance for certain practical routing applications and need to be optimized to significantly improve savings in area, power and performance of the routing network. The present invention discloses several embodiments of the optimized multi-stage pyramid networks for practical routing applications along with their VLSI layout (floor plan) feasibility and simplicity.

The multi-stage pyramid networks considered for optimization in the current invention include: generalized multi-stage networks V(N₁,N₂,d,s), generalized folded multi-stage networks V_(fold)(N₁,N₂,d,s), generalized butterfly fat tree networks V_(bft)(N₁,N₂,d,s), generalized multi-link multi-stage networks V_(mlink)(N₁,N₂,d,s), generalized folded multi-link multi-stage networks V_(fold-mlink)(N₁,N₂,d,s), generalized multi-link butterfly fat tree networks V_(mlink-bft) (N₁,N₂,d,s), generalized hypercube networks V_(hcube)(N₁,N₂,d,s), and generalized cube connected cycles networks V_(ccc)(N₁,N₂,d,s) for s=1, 2, 3 or a whole number in general. Alternatively the optimized multi-stage pyramid networks disclosed in this invention inherit the properties of one or more of these networks, in addition to additional properties that may not be exhibited these networks.

The optimized multi-stage pyramid networks disclosed are applicable for practical routing applications, with several goals such as: 1) all the signals in the design starting from an inlet link of the network to an outlet link of the network need to be setup without blocking. These signals may consist of broadcast, unicast and multicast connections; Each routing resource may need to be used by only one signal or connection; 2) physical area consumed by the routing network to setup all the signals needs to be small; 3) power consumption of the network needs to be small, after the signals are setup. Power may be both static power and dynamic power; 4) Delay of the signal or a connection needs to be small after it is setup through a path using several routing resources in the path. The smaller the delay of the connections will lead to faster performance of the design. Typically delay of the critical connections determines the performance of the design on a given network; 5) Designs need to be not only routed through the network (i.e., all the signals need to be setup from inlet links of the network to the outlet links of the network.), but also the routing needs to be in faster time using efficient routing algorithms; 6) Efficient VLSI layout of the network is also critical and can greatly influence all the other parameters including the area taken up by the network on the chip, total number of wires, length of the wires, delay through the signal paths and hence the maximum clock speed of operation.

The different varieties of multi-stage networks described in various embodiments in the current invention have not been implemented previously on the semiconductor chips. The practical application of these networks includes Field Programmable Gate Array (FPGA) chips. Current commercial FPGA products such as Xilinx's Vertex, Altera's Stratix, Lattice's ECPx implement island-style architecture using mesh and segmented mesh routing interconnects using either full crossbars or sparse crossbars. These routing interconnects consume large silicon area for crosspoints, long wires, large signal propagation delay and hence consume lot of power.

The current invention discloses the optimization and scheduling methods of multi-stage pyramid networks with fast scheduling of connections, for practical routing applications of numerous types of multi-stage networks also using multi-drop links with automatic fabric or network generation given the parameters such as number of inlet links, number outlet links and number of external wires etc. of the fabric or network. The optimizations disclosed in the current invention are applicable to including the numerous generalized multi-stage pyramid networks disclosed in the following patent applications:

1) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized multi-stage networks V(N₁,N₂,d,s) with numerous connection topologies and the scheduling methods are described in detail in the U.S. Pat. No. 8,270,400 that is incorporated by reference above.

2) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized butterfly fat tree networks V_(bft)(N₁,N₂,d,s) with numerous connection topologies and the scheduling methods are described in detail in the U.S. Pat. No. 8,170,040 that is incorporated by reference above.

3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and strictly nonblocking for unicast for generalized multi-link multi-stage networks V_(mlink)(N₁,N₂,d,s) and generalized folded multi-link multi-stage networks V_(fold-mlink)(N₁,N₂,d,s) with numerous connection topologies and the scheduling methods are described in detail in the U.S. Pat. No. 8,363,649 that is incorporated by reference above.

4) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized multi-link butterfly fat tree networks V_(mlink-bft)(N₁,N₂,d,s) with numerous connection topologies and the scheduling methods are described in detail in the U.S. Pat. No. 8,170,040 that is incorporated by reference above.

5) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized folded multi-stage networks V_(fold)(N₁,N₂,d,s) with numerous connection topologies and the scheduling methods are described in detail in the U.S. Pat. No. 8,363,649 that is incorporated by reference above.

6) Strictly nonblocking for arbitrary fan-out multicast and unicast for generalized multi-link multi-stage networks V_(mlink)(N₁,N₂,d,s) and generalized folded multi-link multi-stage networks V_(fold-mlink)(N₁,N₂,d,s) with numerous connection topologies and the scheduling methods are described in detail in the U.S. Pat. No. 8,363,649 that is incorporated by reference above.

7) VLSI layouts of numerous types of multi-stage networks are described in the U.S. Pat. No. 8,269,523 entitled “VLSI LAYOUTS OF FULLY CONNECTED NETWORKS” that is incorporated by reference above.

8) VLSI layouts of numerous types of multi-stage and pyramid networks are described in the U.S. Pat. No. 8,898,611 entitled “VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID NETWORKS WITH LOCALITY EXPLOITATION” that is incorporated by reference above.

9) VLSI layouts of numerous optimized multi-stage and pyramid networks comprising either fully or partially populated switches for practical routing applications with scheduling methods are described in the U.S. Pat. No. 9,374,322 entitled “OPTIMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS FOR PRACTICAL ROUTING APPLICATIONS” that is incorporated by reference above.

10) VLSI layouts of numerous optimized multi-stage and pyramid networks comprising either fully or partially populated switches with connections including multi-drop links for fast scheduling and with scheduling methods are described in the U.S. Pat. No. 9,509,634 entitled “FAST SCHEDULING AND OPTIMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS” that is incorporated by reference above.

Also the optimizations with the VLSI layouts disclosed in the above related patents and in the current invention are also applied to generalized multi-stage pyramid networks V_(p)(N₁,N₂,d,s), generalized folded multi-stage pyramid networks V_(fold-p)(N₁,N₂,d,s), generalized butterfly fat pyramid networks V_(bfp)(N₁,N₂,d,s), generalized multi-link multi-stage pyramid networks V_(mlink-p)(N₁,N₂,d,s), generalized folded multi-link multi-stage pyramid networks V_(fold-mlink-p)(N₁,N₂,d,s), generalized multi-link butterfly fat pyramid networks V_(mlink-bfp)(N₁,N₂,d,s), generalized hypercube networks V_(hcube)(N₁,N₂,d,s) and generalized cube connected cycles networks V_(CCC)(N₁,N₂,d,s) for s=1, 2, 3 or a whole number in general.

Finally the current invention discloses the optimizations and VLSI layouts of multi-stage pyramid networks V_(Comb)(N₁,N₂,d,s) and the optimizations and VLSI layouts of multi-stage pyramid networks V_(D-Comb)(N₁,N₂,d,s) for practical routing applications (particularly to set up broadcast, unicast and multicast connections), where “Comb” denotes the combination of and “D-Comb” denotes the delay optimized combination of an generalized multi-stage networks V(N₁,N₂,d,s), generalized folded multi-stage networks V_(fold)(N₁,N₂,d,s), generalized butterfly fat tree networks V_(bft)(N₁,N₂,d,s), generalized multi-link multi-stage networks V_(mlink)(N₁,N₂,d,s) generalized folded multi-link multi-stage networks V_(fold-mlink)(N₁,N₂,d,s), generalized multi-link butterfly fat tree networks V_(mlink-bft)(N₁,N₂,d,s), generalized multi-stage pyramid networks V_(p)(N₁,N₂,d,s), generalized folded multi-stage pyramid networks V_(fold-p)(N₁,N₂,d,s), generalized butterfly fat pyramid networks V_(bfp)(N₁,N₂,d,s), generalized multi-link multi-stage pyramid networks V_(mlink-p)(N₁,N₂,d,s), generalized folded multi-link multi-stage pyramid networks V_(fold-mlink-p)(N₁,N₂,d,s), generalized multi-link butterfly fat pyramid networks V_(mlink-bfp)(N₁,N₂,d,s), generalized hypercube networks V_(hcube)(N₁,N₂,d,s), and generalized cube connected cycles networks V_(ccc)(N₁,N₂,d,s) for s=1, 2, 3 or a whole number in general. Also “d” in all the networks notations disclosed in the current invention is a whole number and may or may not be constant throughout the network. For example numerous embodiments are built with a variable “d” so that one stage of a ring may have d=2, another stage of the same ring may have d=3 and also the same stage may be built with different d values. In general d is a whole number and may vary from stage to stage with in ring, or from ring to ring in the same partial network, or from one partial network to another partial network.

Multi-Stage Pyramid Network V_(Comb)(N₁,N₂,d,s):

Referring to diagram 100A in FIG. 1A, in one embodiment, an exemplary partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where N₁=200; N₂=400; d=2; and s=1 corresponding to one computational block, with each computational block having 4 inlet links namely I1, I2, I3, and I4; and 2 outlet links namely O1 and O2. And for each computational block the corresponding partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A consists of two rings 110 and 120, where ring 110 consists of “m+1” stages namely (ring 1, stage 0), (ring 1, stage 1), . . . (ring 1, stage “m−1”), and (ring 1, stage “m”), and ring 120 consists of “n+1” stages namely (ring 2, stage 0), (ring 2, stage 1), . . . (ring 2, stage “n−1”), and (ring 2, stage “n”), where “in” and “n” are positive integers.

Ring 110 has inlet links Ri(1,1) and Ri(1,2), and has outlet links Bo(1,1) and Bo(1,2). Ring 120 has inlet links Fi(2,1) and Fi(2,2), and outlet links Bo(2,1) and Bo(2,2). And hence the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A consists of 4 inlet links and 4 outlet links corresponding to the two rings 110 and 120. Outlet link O1 of the computational block is connected to inlet link Ri(1,1) of ring 110 and also inlet link of Fi(2,1) of ring 120. Similarly outlet link O2 of the computational block is connected to inlet link Ri(1,2) of Ring 110 and also inlet link of Fi(2,2) of Ring 120. And outlet link Bo(1,1) of Ring 110 is connected to inlet link I1 of the computational block. Outlet link Bo(1,2) of Ring 110 is connected to inlet link I2 of the computational block. Similarly outlet link Bo(2,1) of Ring 120 is connected to inlet link I3 of the computational block. Outlet link Bo(2,2) of Ring 120 is connected to inlet link I4 of the computational block. Since in this embodiment outlet link O1 of the computational block is connected to both inlet link Ri(1,1) of ring 110 and inlet link Fi(2,1) of ring 120; and outlet link O2 of the computational block is connected to both inlet link Ri(1,2) of ring 110 and inlet link Fi(2,2) of ring 120, the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A consists of 2 inlet links and 4 outlet links.

The two dimensional grid 800 in FIG. 8 illustrates an exemplary arrangement of 100 blocks arranged in 10 rows and 10 columns, in an embodiment. Each row of 2D-grid consisting of 10 block numbers namely the first row consists of the blocks (1,1), (1,2), (1,3), . . . , (1,9), and (1,10). The second row consists of the blocks (2,1), (2,2), (2,3), . . . , (2,9), and (2,10). Similarly 2D-grid 800 consists of 10 rows of each with 10 blocks and finally the tenth row consists of the blocks (10,1), (10,2), (10,3), . . . , (10,9), and (10,10). Each block of 2D-grid 800, in one embodiment, is part of the die area of a semiconductor integrated circuit (hereinafter alternatively referred to as “integrated circuit device” or “IC device”), so that the complete 2D-grid 800 of 100 blocks represents the complete die of the semiconductor integrated circuit. In one embodiment, each block of 2D-grid 800 consists of one of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A with 2 inlet links and 4 outlet links and the corresponding computational block with 4 inlet links and 2 outlet links. For example block (1,1) of 2D-grid 800 consists of one of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A with 2 inlet links and 4 outlet links and the corresponding computational block with 4 inlet links and 2 outlet links. Similarly each of the 100 blocks of 2D-grid 800 has a separate partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A with 2 inlet links and 4 outlet links and the corresponding computational block with 4 inlet links and 2 outlet links. Hence the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to 2D-grid 800 has N₁=200 inlet links and N₂=400 outlet links. And there are 100 computational blocks each one corresponding to one of the blocks with each computational block having 4 inlet links and 2 outlet links. Also the 2D-grid 800 is organized in the fourth quadrant of the 2D-Plane. In other embodiments the 2D-grid 800 may be organized as either first quadrant, or second quadrant or third quadrant of the 2D-Plane.

Referring to partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A in FIG. 1A, the stage (ring 1, stage 0) consists of 4 inputs namely Ri(1,1), Ri(1,2), Ui(1,1), and Ui(1,2); and 4 outputs Bo(1,1), Bo(1,2), Fo(1,1), and Fo(1,2). The stage (ring 1, stage 0) also consists of eight 2:1 multiplexers (A multiplexer is hereinafter called a “mux”) namely R(1,1), R(1,2), F(1,1), F(1,2), U(1,1), U(1,2), B(1,1), and B(1,2). The 2:1 Mux R(1,1) has two inputs namely Ri(1,1) and Bo(1,1) and has one output Ro(1,1). The 2:1 Mux R(1,2) has two inputs namely Ri(1,2) and Bo(1,2) and has one output Ro(1,2). The 2:1 Mux F(1,1) has two inputs namely Ro(1,1) and Ro(1,2) and has one output Fo(1,1). The 2:1 Mux F(1,2) has two inputs namely Ro(1,1) and Ro(1,2) and has one output Fo(1,2).

The 2:1 Mux U(1,1) has two inputs namely Ui(1,1) and Fo(1,1) and has one output Uo(1,1). The 2:1 Mux U(1,2) has two inputs namely Ui(1,2) and Fo(1,2) and has one output Uo(1,2). The 2:1 Mux B(1,1) has two inputs namely Uo(1,1) and Uo(1,2) and has one output Bo(1,1). The 2:1 Mux B(1,2) has two inputs namely Uo(1,1) and Uo(1,2) and has one output Bo(1,2).

The stage (ring 1, stage 1) consists of 4 inputs namely Ri(1,3), Ri(1,4), Ui(1,3), and Ui(1,4); and 4 outputs Bo(1,3), Bo(1,4), Fo(1,3), and Fo(1,4). The stage (ring 1, stage 1) also consists of eight 2:1 Muxes namely R(1,3), R(1,4), F(1,3), F(1,4), U(1,3), U(1,4), B(1,3), and B(1,4). The 2:1 Mux R(1,3) has two inputs namely Ri(1,3) and Bo(1,3) and has one output Ro(1,3). The 2:1 Mux R(1,4) has two inputs namely Ri(1,4) and Bo(1,4) and has one output Ro(1,4). The 2:1 Mux F(1,3) has two inputs namely Ro(1,3) and Ro(1,4) and has one output Fo(1,3). The 2:1 Mux F(1,4) has two inputs namely Ro(1,3) and Ro(1,4) and has one output Fo(1,4).

The 2:1 Mux U(1,3) has two inputs namely Ui(1,3) and Fo(1,3) and has one output Uo(1,3). The 2:1 Mux U(1,4) has two inputs namely Ui(1,4) and Fo(1,4) and has one output Uo(1,4). The 2:1 Mux B(1,3) has two inputs namely Uo(1,3) and Uo(1,4) and has one output Bo(1,3). The 2:1 Mux B(1,4) has two inputs namely Uo(1,3) and Uo(1,4) and has one output Bo(1,4).

The output Fo(1,1) of the stage (ring 1, stage 0) is connected to the input Ri(1,3) of the stage (ring 1, stage 1) which is called hereinafter an internal connection (hereinafter alternatively referred to as “straight link” or “straight middle link”) between two successive stages of a ring. And the output Bo(1,3) of the stage (ring 1, stage 1) is connected to the input Ui(1,1) of the stage (ring 1, stage 0), is another internal connection between stage 0 and stage 1 of the ring 1.

The stage (ring 1, stage “m−1”) consists of 4 inputs namely Fi(1,2m−1), Fi(1,2m), Ui(1,2m−1), and Ui(1,2m); and 4 outputs Bo(1,2m−1), Bo(1,2m), Fo(1,2m−1), and Fo(1,2m). The stage (ring 1, stage “m−1’) also consists of six 2:1 Muxes namely F(1,2m−1), F(1,2m), U(1,2m−1), U(1,2m), B(1,2m−1), and B(1,2m). The 2:1 Mux F(1,2m−1) has two inputs namely Fi(1,2m−1) and Fi(1,2m) and has one output Fo(1,2m−1). The 2:1 Mux F(1,2m) has two inputs namely Fi(1,2m−1) and Fi(1,2m) and has one output Fo(1,2m).

The 2:1 Mux U(1,2m−1) has two inputs namely Ui(1,2m−1) and Fo(1,2m−1) and has one output Uo(1,2m−1). The 2:1 Mux U(1,2m) has two inputs namely Ui(1,2m) and Fo(1,2m) and has one output Uo(1,2m). The 2:1 Mux B(1,2m−1) has two inputs namely Uo(1,2m−1) and Uo(1,2m) and has one output Bo(1,2m−1). The 2:1 Mux B(1,2m) has two inputs namely Uo(1,2m−1) and Uo(1,2m) and has one output Bo(1,2m).

The stage (ring 1, stage “m”) consists of 4 inputs namely Fi(1,2m+1), Fi(1,2m+2), Ui(1,2m+1), and Ui(1,2m+2); and 4 outputs Bo(1,2m+1), Bo(1,2m+2), Fo(1,2m+1), and Fo(1,2m+2). The stage (ring 1, stage “m”) also consists of six 2:1 Muxes namely F(1,2m+1), F(1,2m+2), U(1,2m+1), U(1,2m+2), B(1,2m+1), and B(1,2m+2). The 2:1 Mux F(1,2m+1) has two inputs namely Fi(1,2m+1) and Fi(1,2m+2) and has one output Fo(1,2m+1). The 2:1 Mux F(1,2m+2) has two inputs namely Fi(1,2m+1) and Fi(1,2m+2) and has one output Fo(1,2m+2).

The 2:1 Mux U(1,2m+1) has two inputs namely Ui(1,2m+1) and Fo(1,2m+1) and has one output Uo(1,2m+1). The 2:1 Mux U(1,2m+2) has two inputs namely Ui(1,2m+2) and Fo(1,2m+2) and has one output Uo(1,2m+2). The 2:1 Mux B(1,2m+1) has two inputs namely Uo(1,2m+1) and Uo(1,2m+2) and has one output Bo(1,2m+1). The 2:1 Mux B(1,2m+2) has two inputs namely Uo(1,2m+1) and Uo(1,2m+2) and has one output Bo(1,2m+2).

The output Fo(1,2m−1) of the stage (ring 1, stage “m−1”) is connected to the input Fi(1,2m+1) of the stage (ring 1, stage “m”), is an internal connection between stage “m−1” and stage “m” of the ring 1. And the output Bo(1,2m+1) of the stage (ring 1, stage “m”) is connected to the input Ui(1,2m−1) of the stage (ring 1, stage “m−1”), is another internal connection between stage “m−1” and stage “m” of the ring 1

Just the same way the stages (ring 1, stage 0), (ring 1, stage 1), there are also stages (ring 1, stage 2), (ring 1, stage 3), . . . (ring 1, stage “m−1”), (ring 1, stage “m”) in that order, where the stages from (ring 1, stage 2), (ring 1, stage 3), . . . , (ring 1, stage “m−2”) are not shown in the diagram 100A. Just the same way the two successive stages (ring 1, stage 0) and (ring 1, stage 1) have internal connections between them as described before, any two successive stages have similar internal connections. For example (ring 1, stage 1) and (ring 1, stage 2) have similar internal connections and (ring 1, stage “m−2”) and (ring 1, stage “m−1”) have similar internal connections.

Stage (ring 1, stage 0) is also called hereinafter the “entry stage” or “first stage” of ring 1, since inlet links and outlet links of the computational block are directly connected to stage (ring 1, stage 0). Also stage (ring 1, stage “m”) is hereinafter the “last stage” or “root stage” of ring 1.

The stage (ring 2, stage 0) consists of 4 inputs namely Fi(2,1), Fi(2,2), Ui(2,1), and Ui(2,2); and 4 outputs Bo(2,1), Bo(2,2), Fo(2,1), and Fo(2,2). The stage (ring 2, stage 0) also consists of six 2:1 Muxes namely F(2,1), F(2,2), U(2,1), U(2,2), B(2,1), and B(2,2). The 2:1 Mux F(2,1) has two inputs namely Fi(2,1) and Fi(2,2) and has one output Fo(2,1). The 2:1 Mux F(2,2) has two inputs namely Fi(2,1) and Fi(2,2) and has one output Fo(2,2).

The 2:1 Mux U(2,1) has two inputs namely Ui(2,1) and Fo(2,1) and has one output Uo(2,1). The 2:1 Mux U(2,2) has two inputs namely Ui(2,2) and Fo(2,2) and has one output Uo(2,2). The 2:1 Mux B(2,1) has two inputs namely Uo(2,1) and Uo(2,2) and has one output Bo(2,1). The 2:1 Mux B(2,2) has two inputs namely Uo(2,1) and Uo(2,2) and has one output Bo(2,2).

The stage (ring 2, stage 1) consists of 4 inputs namely Fi(2,3), Fi(2,4), Ui(2,3), and Ui(2,4); and 4 outputs Bo(2,3), Bo(2,4), Fo(2,3), and Fo(2,4). The stage (ring 2, stage 1) also consists of six 2:1 Muxes namely F(2,3), F(2,4), U(2,3), U(2,4), B(2,3), and B(2,4). The 2:1 Mux F(2,3) has two inputs namely Fi(2,3) and Fi(2,4) and has one output Fo(2,3). The 2:1 Mux F(2,4) has two inputs namely Fi(2,3) and Fi(2,4) and has one output Fo(2,4).

The 2:1 Mux U(2,3) has two inputs namely Ui(2,3) and Fo(2,3) and has one output Uo(2,3). The 2:1 Mux U(2,4) has two inputs namely Ui(2,4) and Fo(2,4) and has one output Uo(2,4). The 2:1 Mux B(2,3) has two inputs namely Uo(2,3) and Uo(2,4) and has one output Bo(2,3). The 2:1 Mux B(2,4) has two inputs namely Uo(2,3) and Uo(2,4) and has one output Bo(2,4).

The output Fo(2,1) of the stage (ring 2, stage 0) is connected to the input Fi(2,3) of the stage (ring 2, stage 1), is an internal connection between stage 0 and stage 1 of the ring 2. And the output Bo(2,3) of the stage (ring 2, stage 1) is connected to the input Ui(2,1) of the stage (ring 2, stage 0), is another internal connection between stage 0 and stage 1 of the ring 1.

The stage (ring 2, stage “n−1”) consists of 4 inputs namely Ri(2,2n−1), Ri(2,2n), Ui(1,2n−1), and Ui(1,2n); and 4 outputs Bo(1,2n−1), Bo(1,2n), Fo(1,2n−1), and Fo(1,2n). The stage (ring 2, stage “n−1’) also consists of eight 2:1 Muxes namely R(2,2n−1), R(2,2n), F(2,2n−1), F(1,2n), U(1,2n−1), U(1,2n), B(1,2n−1), and B(1,2n). The 2:1 Mux R(2,2n−1) has two inputs namely Ri(2,2n−1) and Bo(2,2n−1) and has one output Ro(2,2n−1). The 2:1 Mux R(2,2n) has two inputs namely Ri(2,2n) and Bo(2,2n) and has one output Ro(2,2n). The 2:1 Mux F(2,2n−1) has two inputs namely Ro(2,2n−1) and Ro(2,2n) and has one output Fo(2,2n−1). The 2:1 Mux F(2,2n) has two inputs namely Ro(2,2n−1) and Ro(2,2n) and has one output Fo(2,2n).

The 2:1 Mux U(2,2n−1) has two inputs namely Ui(2,2n−1) and Fo(2,2n−1) and has one output Uo(2,2n−1). The 2:1 Mux U(2,2n) has two inputs namely Ui(2,2n) and Fo(2,2n) and has one output Uo(2,2n). The 2:1 Mux B(2,2n−1) has two inputs namely Uo(2,2n−1) and Uo(2,2n) and has one output Bo(2,2n−1). The 2:1 Mux B(2,2n) has two inputs namely Uo(2,2n−1) and Uo(2,2n) and has one output Bo(2,2n).

The stage (ring 2, stage “n”) consists of 4 inputs namely Ri(2,2n+1), Ri(2,2n+2), Ui(2,2n+1), and Ui(2,2n+2); and 4 outputs Bo(2,2n+1), Bo(2,2n+2), Fo(2,2n+1), and Fo(2,2n+2). The stage (ring 2, stage “n”) also consists of eight 2:1 Muxes namely R(2,2n+1), R(2,2n+2), F(2,2n+1), F(2,2n+2), U(2,2n+1), U(2,2n+2), B(2,2n+1), and B(2,2n+2). The 2:1 Mux R(2,2n+1) has two inputs namely Ri(2,2n+1) and Bo(2,2n+1) and has one output Ro(2,2n+1). The 2:1 Mux R(2,2n+2) has two inputs namely Ri(2,2n+2) and Bo(2,2n+2) and has one output Ro(2,2n+2). The 2:1 Mux F(2,2n+1) has two inputs namely Ro(2,2n+1) and Ro(2,2n+2) and has one output Fo(2,2n+1). The 2:1 Mux F(2,2n+2) has two inputs namely Ro(2,2n+1) and Ro(2,2n+2) and has one output Fo(2,2n+2).

The 2:1 Mux U(2,2n+1) has two inputs namely Ui(2,2n+1) and Fo(2,2n+1) and has one output Uo(2,2n+1). The 2:1 Mux U(2,2n+2) has two inputs namely Ui(2,2n+2) and Fo(2,2n+2) and has one output Uo(2,2n+2). The 2:1 Mux B(2,2n+1) has two inputs namely Uo(2,2n+1) and Uo(2,2n+2) and has one output Bo(2,2n+1). The 2:1 Mux B(2,2n+2) has two inputs namely Uo(2,2n+1) and Uo(2,2n+2) and has one output Bo(2,2n+2).

The output Fo(2,2n−1) of the stage (ring 2, stage “n−1”) is connected to the input Ri(2,2n+1) of the stage (ring 2, stage “n”), is an internal connection between stage “n−1” and stage “n” of the ring 1. And the output Bo(2,2n+1) of the stage (ring 2, stage “n”) is connected to the input Ui(2,2n−1) of the stage (ring 2, stage “n−1”), is another internal connection between stage “n−1” and stage “n” of the ring 1.

Each stage of a ring of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A consists of 4 inputs and 4 outputs. Even though the stages (ring 1, stage 0), (ring 1, stage 1), (ring 2, stage “n−1”), and (ring 2, stage “n”) each have eight 2:1 muxes, and the stages (ring 2, stage 0), (ring 2, stage 1), (ring 1, stage “m−1”), and (ring 1, stage “m”) each have six 2:1 muxes, in other embodiments any of these stages can be one of the four by four switch diagrams namely 200A of FIG. 2A, 200B of FIG. 2B, 200C of FIG. 2C, 200D of FIG. 2D, 200G of FIG. 2G, 200H of FIG. 2H, 200I of FIG. 2I, 200J of FIG. 2J, or one of the eight by four switch diagrams namely 200E of FIG. 2E, 200F of FIG. 2F, or fourteen by six switch diagram 200K of FIG. 2K, or six by six switch diagram 200L of FIG. 2L, or eight by six switch diagram 200M of FIG. 2M, or twelve by six switch diagram 200N of FIG. 2N.

Referring to diagram 100B in FIG. 1B, in one embodiment, an exemplary partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where N₁=400; N₂=800; d=2; and s=1 corresponding to one computational block, with each computational block having 8 inlet links namely I1, I2, I3, I4, I5, I6, I7, and I8; and 4 outlet links namely O1, O2, O3, and O4. And for each computational block the corresponding partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B consists of two rings 110 and 120, where ring 110 consists of “m+1” stages namely (ring 1, stage 0), (ring 1, stage 1), . . . (ring 1, stage “m−1”), and (ring 1, stage “m”), and ring 120 consists of “n+1” stages namely (ring 2, stage 0), (ring 2, stage 1), . . . (ring 2, stage “n−1”), and (ring 2, stage “n”), where “in” and “n” are positive integers.

Ring 110 has inlet links Ri(1,1) and Ri(1,2) from the left-hand side, and has outlet links Bo(1,1) and Bo(1,2) from left-hand side. Ring 110 also has inlet links Ui(1,2m+1) and Ui(1,2m+2) from the right-hand side, and has outlet links Fo(1,2m+1) and Fo(1,2m+2) from right-hand side. Ring 120 has inlet links Fi(2,1) and Fi(2,2) from left-hand side, and outlet links Bo(2,1) and Bo(2,2) from left-hand side. Ring 120 also has inlet links Ui(2,2n+1) and Ui(2,2n+2) from the right-hand side, and has outlet links Fo(2,2n+1) and Fo(2,2n+2) from right-hand side.

And the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B consists of 8 inlet links and 4 outlet links corresponding to the two rings 110 and 120. From left-hand side, outlet link O1 of the computational block is connected to inlet link Ri(1,1) of ring 110 and also inlet link of Fi(2,1) of ring 120. Similarly from left-hand side, outlet link O2 of the computational block is connected to inlet link Ri(1,2) of Ring 110 and also inlet link of Fi(2,2) of Ring 120. And from left-hand side, outlet link Bo(1,1) of Ring 110 is connected to inlet link I1 of the computational block. From left-hand side, Outlet link Bo(1,2) of Ring 110 is connected to inlet link I2 of the computational block. Similarly from left-hand side, outlet link Bo(2,1) of Ring 120 is connected to inlet link I3 of the computational block. From left-hand side, outlet link Bo(2,2) of Ring 120 is connected to inlet link I4 of the computational block.

From right-hand side, outlet link O3 of the computational block is connected to inlet link Ui(1,2m+1) of ring 110 and also inlet link of Ui(2,2n+1) of ring 120. Similarly from right-hand side, outlet link O4 of the computational block is connected to inlet link Ui(1,2m+2) of Ring 110 and also inlet link of Ui(2,2n+2) of Ring 120. And from right-hand side, outlet link Fo(1,2m+1) of Ring 110 is connected to inlet link I5 of the computational block. From right-hand side, outlet link Fo(1,2m+2) of Ring 110 is connected to inlet link I6 of the computational block. Similarly from right-hand side, outlet link Fo(2,2n+1) of Ring 120 is connected to inlet link I7 of the computational block. From right-hand side, outlet link Fo(2,2n+2) of Ring 120 is connected to inlet link I8 of the computational block.

Since in this embodiment outlet link O1 of the computational block is connected to both inlet link Ri(1,1) of ring 110 and inlet link Fi(2,1) of ring 120; outlet link O2 of the computational block is connected to both inlet link Ri(1,2) of ring 110 and inlet link Fi(2,2) of ring 120; outlet link O3 of the computational block is connected to both inlet link Ui(1,2m+1) of ring 110 and inlet link Ui(2,2n+1) of ring 120; and outlet link O4 of the computational block is connected to both inlet link Ui(1,2m+2) of ring 110 and inlet link Ui(2,2n+2) of ring 120, the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B consists of 4 inlet links and 8 outlet links.

Referring to two dimensional grid 800 in FIG. 8 illustrates, in another embodiment, each block of 2D-grid 800 consists of one of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B with 4 inlet links and 8 outlet links and the corresponding computational block with 8 inlet links and 4 outlet links. For example block (1,1) of 2D-grid 800 consists of one of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B with 4 inlet links and 8 outlet links and the corresponding computational block with 8 inlet links and 4 outlet links. Similarly each of the 100 blocks of 2D-grid 800 has a separate partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B with 4 inlet links and 8 outlet links and the corresponding computational block with 8 inlet links and 4 outlet links. Hence the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to 2D-grid 800 has N₁=400 inlet links and N₂=800 outlet links. Since there are 100 computational blocks each one corresponding to one of the blocks with each computational block having 8 inlet links and 4 outlet links. Also the 2D-grid 800 is organized in the fourth quadrant of the 2D-Plane. In other embodiments the 2D-grid 800 may be organized as either first quadrant, or second quadrant or third quadrant of the 2D-Plane.

Referring to partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B in FIG. 1B, the stage (ring 1, stage 0) consists of 4 inputs namely Ri(1,1), Ri(1,2), Ui(1,1), and Ui(1,2); and 4 outputs Bo(1,1), Bo(1,2), Fo(1,1), and Fo(1,2). The stage (ring 1, stage 0) also consists of eight 2:1 multiplexers (A multiplexer is hereinafter called a “mux”) namely R(1,1), R(1,2), F(1,1), F(1,2), U(1,1), U(1,2), B(1,1), and B(1,2). The 2:1 Mux R(1,1) has two inputs namely Ri(1,1) and Bo(1,1) and has one output Ro(1,1). The 2:1 Mux R(1,2) has two inputs namely Ri(1,2) and Bo(1,2) and has one output Ro(1,2). The 2:1 Mux F(1,1) has two inputs namely Ro(1,1) and Ro(1,2) and has one output Fo(1,1). The 2:1 Mux F(1,2) has two inputs namely Ro(1,1) and Ro(1,2) and has one output Fo(1,2).

The 2:1 Mux U(1,1) has two inputs namely Ui(1,1) and Fo(1,1) and has one output Uo(1,1). The 2:1 Mux U(1,2) has two inputs namely Ui(1,2) and Fo(1,2) and has one output Uo(1,2). The 2:1 Mux B(1,1) has two inputs namely Uo(1,1) and Uo(1,2) and has one output Bo(1,1). The 2:1 Mux B(1,2) has two inputs namely Uo(1,1) and Uo(1,2) and has one output Bo(1,2).

The stage (ring 1, stage 1) consists of 4 inputs namely Ri(1,3), Ri(1,4), Ui(1,3), and Ui(1,4); and 4 outputs Bo(1,3), Bo(1,4), Fo(1,3), and Fo(1,4). The stage (ring 1, stage 1) also consists of eight 2:1 Muxes namely R(1,3), R(1,4), F(1,3), F(1,4), U(1,3), U(1,4), B(1,3), and B(1,4). The 2:1 Mux R(1,3) has two inputs namely Ri(1,3) and Bo(1,3) and has one output Ro(1,3). The 2:1 Mux R(1,4) has two inputs namely Ri(1,4) and Bo(1,4) and has one output Ro(1,4). The 2:1 Mux F(1,3) has two inputs namely Ro(1,3) and Ro(1,4) and has one output Fo(1,3). The 2:1 Mux F(1,4) has two inputs namely Ro(1,3) and Ro(1,4) and has one output Fo(1,4).

The 2:1 Mux U(1,3) has two inputs namely Ui(1,3) and Fo(1,3) and has one output Uo(1,3). The 2:1 Mux U(1,4) has two inputs namely Ui(1,4) and Fo(1,4) and has one output Uo(1,4). The 2:1 Mux B(1,3) has two inputs namely Uo(1,3) and Uo(1,4) and has one output Bo(1,3). The 2:1 Mux B(1,4) has two inputs namely Uo(1,3) and Uo(1,4) and has one output Bo(1,4).

The output Fo(1,1) of the stage (ring 1, stage 0) is connected to the input Ri(1,3) of the stage (ring 1, stage 1) which is called hereinafter an internal connection between two successive stages of a ring. And the output Bo(1,3) of the stage (ring 1, stage 1) is connected to the input Ui(1,1) of the stage (ring 1, stage 0), is another internal connection between stage 0 and stage 1 of the ring 1.

The stage (ring 1, stage “m−1”) consists of 4 inputs namely Fi(1,2m−1), Fi(1,2m), Ui(1,2m−1), and Ui(1,2m); and 4 outputs Bo(1,2m−1), Bo(1,2m), Fo(1,2m−1), and Fo(1,2m). The stage (ring 1, stage “m−1’) also consists of six 2:1 Muxes namely F(1,2m−1), F(1,2m), U(1,2m−1), U(1,2m), B(1,2m−1), and B(1,2m). The 2:1 Mux F(1,2m−1) has two inputs namely Fi(1,2m−1) and Fi(1,2m) and has one output Fo(1,2m−1). The 2:1 Mux F(1,2m) has two inputs namely Fi(1,2m−1) and Fi(1,2m) and has one output Fo(1,2m).

The 2:1 Mux U(1,2m−1) has two inputs namely Ui(1,2m−1) and Fo(1,2m−1) and has one output Uo(1,2m−1). The 2:1 Mux U(1,2m) has two inputs namely Ui(1,2m) and Fo(1,2m) and has one output Uo(1,2m). The 2:1 Mux B(1,2m−1) has two inputs namely Uo(1,2m−1) and Uo(1,2m) and has one output Bo(1,2m−1). The 2:1 Mux B(1,2m) has two inputs namely Uo(1,2m−1) and Uo(1,2m) and has one output Bo(1,2m).

The stage (ring 1, stage “m”) consists of 4 inputs namely Fi(1,2m+1), Fi(1,2m+2), Ui(1,2m+1), and Ui(1,2m+2); and 4 outputs Bo(1,2m+1), Bo(1,2m+2), Fo(1,2m+1), and Fo(1,2m+2). The stage (ring 1, stage “m”) also consists of six 2:1 Muxes namely F(1,2m+1), F(1,2m+2), U(1,2m+1), U(1,2m+2), B(1,2m+1), and B(1,2m+2). The 2:1 Mux F(1,2m+1) has two inputs namely Fi(1,2m+1) and Fi(1,2m+2) and has one output Fo(1,2m+1). The 2:1 Mux F(1,2m+2) has two inputs namely Fi(1,2m+1) and Fi(1,2m+2) and has one output Fo(1,2m+2).

The 2:1 Mux U(1,2m+1) has two inputs namely Ui(1,2m+1) and Fo(1,2m+1) and has one output Uo(1,2m+1). The 2:1 Mux U(1,2m+2) has two inputs namely Ui(1,2m+2) and Fo(1,2m+2) and has one output Uo(1,2m+2). The 2:1 Mux B(1,2m+1) has two inputs namely Uo(1,2m+1) and Uo(1,2m+2) and has one output Bo(1,2m+1). The 2:1 Mux B(1,2m+2) has two inputs namely Uo(1,2m+1) and Uo(1,2m+2) and has one output Bo(1,2m+2).

The output Fo(1,2m−1) of the stage (ring 1, stage “m−1”) is connected to the input Fi(1,2m+1) of the stage (ring 1, stage “m”), is an internal connection between stage “m−1” and stage “m” of the ring 1. And the output Bo(1,2m+1) of the stage (ring 1, stage “m”) is connected to the input Ui(1,2m−1) of the stage (ring 1, stage “m−1”), is another internal connection between stage “m−1” and stage “m” of the ring 1

Just the same way the stages (ring 1, stage 0), (ring 1, stage 1), there are also stages (ring 1, stage 2), (ring 1, stage 3), . . . (ring 1, stage “m−1”), (ring 1, stage “m”) in that order, where the stages from (ring 1, stage 2), (ring 1, stage 3), . . . , (ring 1, stage “m−2”) are not shown in the diagram 100B. Just the same way the two successive stages (ring 1, stage 0) and (ring 1, stage 1) have internal connections between them as described before, any two successive stages have similar internal connections. For example (ring 1, stage 1) and (ring 1, stage 2) have similar internal connections and (ring 1, stage “m−2”) and (ring 1, stage “m−1”) have similar internal connections.

Stage (ring 1, stage 0) is also called hereinafter the “entry stage” or “first stage” of ring 1, since inlet links and outlet links of the computational block are directly connected to stage (ring 1, stage 0). Also stage (ring 1, stage “m”) is hereinafter the “last stage” or “root stage” of ring 1.

The stage (ring 2, stage 0) consists of 4 inputs namely Fi(2,1), Fi(2,2), Ui(2,1), and Ui(2,2); and 4 outputs Bo(2,1), Bo(2,2), Fo(2,1), and Fo(2,2). The stage (ring 2, stage 0) also consists of six 2:1 Muxes namely F(2,1), F(2,2), U(2,1), U(2,2), B(2,1), and B(2,2). The 2:1 Mux F(2,1) has two inputs namely Fi(2,1) and Fi(2,2) and has one output Fo(2,1). The 2:1 Mux F(2,2) has two inputs namely Fi(2,1) and Fi(2,2) and has one output Fo(2,2).

The 2:1 Mux U(2,1) has two inputs namely Ui(2,1) and Fo(2,1) and has one output Uo(2,1). The 2:1 Mux U(2,2) has two inputs namely Ui(2,2) and Fo(2,2) and has one output Uo(2,2). The 2:1 Mux B(2,1) has two inputs namely Uo(2,1) and Uo(2,2) and has one output Bo(2,1). The 2:1 Mux B(2,2) has two inputs namely Uo(2,1) and Uo(2,2) and has one output Bo(2,2).

The stage (ring 2, stage 1) consists of 4 inputs namely Fi(2,3), Fi(2,4), Ui(2,3), and Ui(2,4); and 4 outputs Bo(2,3), Bo(2,4), Fo(2,3), and Fo(2,4). The stage (ring 2, stage 1) also consists of six 2:1 Muxes namely F(2,3), F(2,4), U(2,3), U(2,4), B(2,3), and B(2,4). The 2:1 Mux F(2,3) has two inputs namely Fi(2,3) and Fi(2,4) and has one output Fo(2,3). The 2:1 Mux F(2,4) has two inputs namely Fi(2,3) and Fi(2,4) and has one output Fo(2,4).

The 2:1 Mux U(2,3) has two inputs namely Ui(2,3) and Fo(2,3) and has one output Uo(2,3). The 2:1 Mux U(2,4) has two inputs namely Ui(2,4) and Fo(2,4) and has one output Uo(2,4). The 2:1 Mux B(2,3) has two inputs namely Uo(2,3) and Uo(2,4) and has one output Bo(2,3). The 2:1 Mux B(2,4) has two inputs namely Uo(2,3) and Uo(2,4) and has one output Bo(2,4).

The output Fo(2,1) of the stage (ring 2, stage 0) is connected to the input Fi(2,3) of the stage (ring 2, stage 1), is an internal connection between stage 0 and stage 1 of the ring 2. And the output Bo(2,3) of the stage (ring 2, stage 1) is connected to the input Ui(2,1) of the stage (ring 2, stage 0), is another internal connection between stage 0 and stage 1 of the ring 1.

The stage (ring 2, stage “n−1”) consists of 4 inputs namely Ri(2,2n−1), Ri(2,2n), Ui(1,2n−1), and Ui(1,2n); and 4 outputs Bo(1,2n−1), Bo(1,2n), Fo(1,2n−1), and Fo(1,2n). The stage (ring 2, stage “n−1’) also consists of eight 2:1 Muxes namely R(2,2n−1), R(2,2n), F(2,2n−1), F(1,2n), U(1,2n−1), U(1,2n), B(1,2n−1), and B(1,2n). The 2:1 Mux R(2,2n−1) has two inputs namely Ri(2,2n−1) and Bo(2,2n−1) and has one output Ro(2,2n−1). The 2:1 Mux R(2,2n) has two inputs namely Ri(2,2n) and Bo(2,2n) and has one output Ro(2,2n). The 2:1 Mux F(2,2n−1) has two inputs namely Ro(2,2n−1) and Ro(2,2n) and has one output Fo(2,2n−1). The 2:1 Mux F(2,2n) has two inputs namely Ro(2,2n−1) and Ro(2,2n) and has one output Fo(2,2n).

The 2:1 Mux U(2,2n−1) has two inputs namely Ui(2,2n−1) and Fo(2,2n−1) and has one output Uo(2,2n−1). The 2:1 Mux U(2,2n) has two inputs namely Ui(2,2n) and Fo(2,2n) and has one output Uo(2,2n). The 2:1 Mux B(2,2n−1) has two inputs namely Uo(2,2n−1) and Uo(2,2n) and has one output Bo(2,2n−1). The 2:1 Mux B(2,2n) has two inputs namely Uo(2,2n−1) and Uo(2,2n) and has one output Bo(2,2n).

The stage (ring 2, stage “n”) consists of 4 inputs namely Ri(2,2n+1), Ri(2,2n+2), Ui(2,2n+1), and Ui(2,2n+2); and 4 outputs Bo(2,2n+1), Bo(2,2n+2), Fo(2,2n+1), and Fo(2,2n+2). The stage (ring 2, stage “n”) also consists of eight 2:1 Muxes namely R(2,2n+1), R(2,2n+2), F(2,2n+1), F(2,2n+2), U(2,2n+1), U(2,2n+2), B(2,2n+1), and B(2,2n+2). The 2:1 Mux R(2,2n+1) has two inputs namely Ri(2,2n+1) and Bo(2,2n+1) and has one output Ro(2,2n+1). The 2:1 Mux R(2,2n+2) has two inputs namely Ri(2,2n+2) and Bo(2,2n+2) and has one output Ro(2,2n+2). The 2:1 Mux F(2,2n+1) has two inputs namely Ro(2,2n+1) and Ro(2,2n+2) and has one output Fo(2,2n+1). The 2:1 Mux F(2,2n+2) has two inputs namely Ro(2,2n+1) and Ro(2,2n+2) and has one output Fo(2,2n+2).

The 2:1 Mux U(2,2n+1) has two inputs namely Ui(2,2n+1) and Fo(2,2n+1) and has one output Uo(2,2n+1). The 2:1 Mux U(2,2n+2) has two inputs namely Ui(2,2n+2) and Fo(2,2n+2) and has one output Uo(2,2n+2). The 2:1 Mux B(2,2n+1) has two inputs namely Uo(2,2n+1) and Uo(2,2n+2) and has one output Bo(2,2n+1). The 2:1 Mux B(2,2n+2) has two inputs namely Uo(2,2n+1) and Uo(2,2n+2) and has one output Bo(2,2n+2).

The output Fo(2,2n−1) of the stage (ring 2, stage “n−1”) is connected to the input Ri(2,2n+1) of the stage (ring 2, stage “n”), is an internal connection between stage “n−1” and stage “n” of the ring 1. And the output Bo(2,2n+1) of the stage (ring 2, stage “n”) is connected to the input Ui(2,2n−1) of the stage (ring 2, stage “n−1”), is another internal connection between stage “n−1” and stage “n” of the ring 1.

Each stage of a ring of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B consists of 4 inputs and 4 outputs. Even though each stage has four 4:1 muxes, in other embodiments any of these stages can be one of the four by four switch diagrams namely 200A of FIG. 2A, 200B of FIG. 2B, 200C of FIG. 2C, 200D of FIG. 2D, 200G of FIG. 2G, 200H of FIG. 2H, 200I of FIG. 2I, 200J of FIG. 2J, or one of the eight by four switch diagrams namely 200E of FIG. 2E, 200F of FIG. 2F, or fourteen by six switch diagram 200K of FIG. 2K, or six by six switch diagram 200L of FIG. 2L, or eight by six switch diagram 200M of FIG. 2M, or twelve by six switch diagram 200N of FIG. 2N.

In general, any ring of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) may have inputs and outputs connected from computational block from either only from left-hand side as in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A; or only from right-hand side; or from both left-hand and right-hand sides as in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B.

Referring to diagram 100C in FIG. 1C, in one embodiment, an exemplary partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where N₁=400; N₂=1600; d=2; and s=1 corresponding to one computational block, with each computational block having 16 inlet links namely I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, and I16; and 4 outlet links namely O1, O2, O3, and O4. And for each computational block the corresponding partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C consists of two slices namely slice 1 and slice 2. Slice 1 consists of two rings namely (slice 1, ring 1) and (slice 1, ring 2). Similarly slice 2 consists of two rings namely (slice 2, ring 1) and (slice 2, ring 2).

The ring (slice 1, ring 1) consists of “m+1” stages namely (slice 1, ring 1, stage 0), (slice 1, ring 1, stage 1), . . . (slice 1, ring 1, stage “m−1”), and (slice 1, ring 1, stage “m”). And the ring (slice 1, ring 2) consists of “n+1” stages namely (slice 1, ring 2, stage 0), (slice 1, ring 2, stage 1), . . . (slice 1, ring 2, stage “n−1”), and (slice 1, ring 2, stage “n”), where “m” and “n” are positive integers.

Similarly the ring (slice 2, ring 1) consists of “x+1” stages namely (slice 2, ring 1, stage 0), (slice 2, ring 1, stage 1), . . . (slice 2, ring 1, stage “x−1”), and (slice 2, ring 1, stage “x”). And the ring (slice 2, ring 2) consists of “y+1” stages namely (slice 2, ring 2, stage 0), (slice 2, ring 2, stage 1), . . . (slice 2, ring 2, stage “y−1”), and (slice 2, ring 2, stage “y”), where “x” and “y” are positive integers.

In general “m” may be or may not be equal to “x” and “n” may be or may not be equal to “y”. Also in general, “m” may be or may not be equal to “n” and “x” may be or may not be equal to “y”.

Ring (slice 1, ring 1) has inlet links Ri(1,1,1) and Ri(1,1,2) from the left-hand side, and has outlet links Bo(1,1,1) and Bo(1,1,2) from left-hand side. Ring (slice 1, ring 1) also has inlet links Ui(1,1,2m+1) and Ui(1,1,2m+2) from the right-hand side, and has outlet links Fo(1,1,2m+1) and Fo(1,1,2m+2) from right-hand side. Ring (slice 1, ring 2) has inlet links Ri(1,2,1) and Ri(1,2,2) from left-hand side, and outlet links Bo(1,2,1) and Bo(1,2,2) from left-hand side. Ring (slice 1, ring 2) also has inlet links Ui(1,2,2n+1) and Ui(1,2,2n+2) from the right-hand side, and has outlet links Fo(1,2,2n+1) and Fo(1,2,2n+2) from right-hand side.

Ring (slice 2, ring 1) has inlet links Ri(2,1,1) and Ri(2,1,2) from the left-hand side, and has outlet links Bo(2,1,1) and Bo(2,1,2) from left-hand side. Ring (slice 2, ring 1) also has inlet links Ui(2,1,2x+1) and Ui(2,1,2x+2) from the right-hand side, and has outlet links Fo(2,1,2x+1) and Fo(2,1,2x+2) from right-hand side. Ring (slice 2, ring 2) has inlet links Ri(2,2,1) and Ri(2,2,2) from left-hand side, and outlet links Bo(2,2,1) and Bo(2,2,2) from left-hand side. Ring (slice 2, ring 2) also has inlet links Ui(2,2,2y+1) and Ui(2,2,2y+2) from the right-hand side, and has outlet links Fo(2,2,2y+1) and Fo(2,2,2y+2) from right-hand side.

And the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C consists of 16 inlet links and 4 outlet links corresponding to the two slices slice 1 and slice 2. From left-hand side, outlet link O1 of the computational block is connected to inlet link Ri(1,1,1) of ring (slice 1, ring 1) and also inlet link of Ri(1,2,1) of ring (slice 1, ring 2). Similarly from left-hand side, outlet link O2 of the computational block is connected to inlet link Ri(1,1,2) of Ring (slice 1, ring 1) and also inlet link of Ri(1,2,2) of Ring (slice 1, ring 2). And from left-hand side, outlet link Bo(1,1,1) of Ring (slice 1, ring 1) is connected to inlet link I1 of the computational block. From left-hand side, Outlet link Bo(1,1,2) of Ring (slice 1, ring 1) is connected to inlet link I2 of the computational block. Similarly from left-hand side, outlet link Bo(1,2,1) of Ring (slice 1, ring 2) is connected to inlet link I3 of the computational block. From left-hand side, outlet link Bo(1,2,2) of Ring (slice 1, ring 2) is connected to inlet link I4 of the computational block.

From right-hand side, outlet link O1 of the computational block is connected to inlet link Ui(1,1,2m+1) of ring (slice 1, ring 1) and also inlet link of Ui(1,2,2n+1) of ring (slice 1, ring 2). Similarly from right-hand side, outlet link O2 of the computational block is connected to inlet link Ui(1,1,2m+2) of Ring (slice 1, ring 1) and also inlet link of Ui(1,2,2n+2) of Ring (slice 1, ring 2). And from right-hand side, outlet link Fo(1,1,2m+1) of Ring (slice 1, ring 1) is connected to inlet link I5 of the computational block. From right-hand side, outlet link Fo(1,1,2m+2) of Ring (slice 1, ring 1) is connected to inlet link I6 of the computational block. Similarly from right-hand side, outlet link Fo(1,2,2n+1) of Ring (slice 1, ring 2) is connected to inlet link I7 of the computational block. From right-hand side, outlet link Fo(1,2,2n+2) of Ring (slice 1, ring 2) is connected to inlet link I8 of the computational block.

From left-hand side, outlet link O3 of the computational block is connected to inlet link Ri(2,1,1) of ring (slice 2, ring 1) and also inlet link of Ri(2,2,1) of ring (slice 2, ring 2). Similarly from left-hand side, outlet link O4 of the computational block is connected to inlet link Ri(2,1,2) of Ring (slice 2, ring 1) and also inlet link of Ri(2,2,2) of Ring (slice 2, ring 2). And from left-hand side, outlet link Bo(2,1,1) of Ring (slice 2, ring 1) is connected to inlet link I9 of the computational block. From left-hand side, Outlet link Bo(2,1,2) of Ring (slice 2, ring 1) is connected to inlet link I10 of the computational block. Similarly from left-hand side, outlet link Bo(2,2,1) of Ring (slice 2, ring 2) is connected to inlet link I11 of the computational block. From left-hand side, outlet link Bo(2,2,2) of Ring (slice 2, ring 2) is connected to inlet link I12 of the computational block.

From right-hand side, outlet link O3 of the computational block is connected to inlet link Ui(2,1,2x+1) of ring (slice 2, ring 1) and also inlet link of Ui(2,2,2y+1) of ring (slice 2, ring 2). Similarly from right-hand side, outlet link O4 of the computational block is connected to inlet link Ui(2,1,2x+2) of Ring (slice 2, ring 1) and also inlet link of Ui(2,2,2y+2) of Ring (slice 2, ring 2). And from right-hand side, outlet link Fo(2,1,2x+1) of Ring (slice 2, ring 1) is connected to inlet link I13 of the computational block. From right-hand side, outlet link Fo(2,1,2x+2) of Ring (slice 2, ring 1) is connected to inlet link I14 of the computational block. Similarly from right-hand side, outlet link Fo(2,2,2y+1) of Ring (slice 2, ring 2) is connected to inlet link I15 of the computational block. From right-hand side, outlet link Fo(2,2,2y+2) of Ring (slice 2, ring 2) is connected to inlet link I16 of the computational block.

In this embodiment outlet links O1 and O2 of the computational block are connected only to slice 1. Similarly outlet links O3 and O4 of the computational block are connected only to slice 2.

Referring to two dimensional grid 800 in FIG. 8 illustrates, in another embodiment, each block of 2D-grid 800 consists of one of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C with 4 inlet links and 16 outlet links and the corresponding computational block with 16 inlet links and 4 outlet links. For example block (1,1) of 2D-grid 800 consists of one of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C with 4 inlet links and 16 outlet links and the corresponding computational block with 16 inlet links and 4 outlet links. Similarly each of the 100 blocks of 2D-grid 800 has a separate partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C with 4 inlet links and 16 outlet links and the corresponding computational block with 16 inlet links and 4 outlet links. Hence the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to 2D-grid 800 has N₁=400 inlet links and N₂=1600 outlet links. Since there are 100 computational blocks each one corresponding to one of the blocks with each computational block having 16 inlet links and 4 outlet links. Also the 2D-grid 800 is organized in the fourth quadrant of the 2D-Plane. In other embodiments the 2D-grid 800 may be organized as either first quadrant, or second quadrant or third quadrant of the 2D-Plane.

Referring to partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C in FIG. 1C, the stage (slice 1, ring 1, stage 0) consists of 8 inputs namely Ri(1,1,1), Ri(1,1,2), Ui(1,1,1), Ui(1,1,2), J(1,1,1), K(1,1,1), L(1,1,1), and M(1,1,1); and 4 outputs Bo(1,1,1), Bo(1,1,2), Fo(1,1,1), and Fo(1,1,2). The stage (slice 1, ring “1”, stage “0”) also consists of four 4:1 Muxes namely F(1,1,1), F(1,1,2), B(1,1,1), and B(1,1,2). The 4:1 Mux F(1,1,1) has four inputs namely Ri(1,1,1), Ri(1,1,2), Ui(1,1,2), and J(1,1,1), and has one output Fo(1,1,1). The 4:1 Mux F(1,1,2) has four inputs namely Ri(1,1,1), Ri(1,1,2), Ui(1,1,1), and K(1,1,1), and has one output Fo(1,1,2).

The 4:1 Mux B(1,1,1) has four inputs namely Ui(1,1,1), Ui(1,1,2), Ri(1,1,2), and L(1,1,1), and has one output Bo(1,1,1). The 4:1 Mux B(1,1,2) has four inputs namely Ui(1,1,1), Ui(1,1,2), Ri(1,1,1) and M(1,1,1), and has one output Bo(1,1,2). In different embodiments the inputs J(1,1,1), K(1,1,1), L(1,1,1), and M(1,1,1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (slice 1, ring 1, stage “m”) consists of 8 inputs namely Ri(1,1,2m+1), Ri(1,1,2m+2), Ui(1,1,2m+1), Ui(1,1,2m+2), J(1,1,m+1), K(1,1,m+1), L(1,1,m+1), and M(1,1,m+1); and 4 outputs Bo(1,1,2m+1), Bo(1,1,2m+2), Fo(1,1,2m+1), and Fo(1,1,2m+2). The stage (slice 1, ring 1, stage “m”) also consists of four 4:1 Muxes namely F(1,1,2m+1), F(1,1,2m+2), B(1,1,2m+1), and B(1,1,2m+2). The 4:1 Mux F(1,1,2m+1) has four inputs namely Ri(1,1,2m+1), Ri(1,1,2m+2), Ui(1,1,2m+2), and J(1,1,m+1), and has one output Fo(1,1,2m+1). The 4:1 Mux F(1,1,2m+2) has four inputs namely Ri(1,1,2m+1), Ri(1,1,2m+2), Ui(1,1,2m+1), and K(1,1,m+1), and has one output Fo(1,1,2m+2).

The 4:1 Mux B(1,1,2m+1) has four inputs namely Ui(1,1,2m+1), Ui(1,1,2m+2), Ri(1,1,2m+2), and L(1,1,m+1), and has one output Bo(1,1,2m+1). The 4:1 Mux B(1,1,2m+2) has four inputs namely Ui(1,1,2m+1), Ui(1,1,2m+2), Ri(1,1,2m+1) and M(1,1,m+1), and has one output Bo(1,1,2m+2). In different embodiments the inputs J(1,1,m+1), K(1,1,m+1), L(1,1,m+1), and M(1,1,m+1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

Just the same way the stage (slice 1, ring 1, stage 0), there are also stages (slice 1, ring 1, stage 1), (slice 1, ring 1, stage 2), (slice 1, ring 1, stage 3), . . . (slice 1, ring 1, stage “m−1”), (slice 1, ring 1, stage “m”) in that order, where the stages from (slice 1, ring 1, stage 1), (slice 1, ring 1, stage 2), . . . , (slice 1, ring 1, stage “m−1”) are not shown in the diagram 100C.

Referring to diagram 100C5 in FIG. 1C5 illustrates specific details of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C in FIG. 1C, particularly the internal connections between two successive stages of any ring of a slice, in one embodiment. The stage (slice “c”, ring “d”, stage “e”) consists of 8 inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), Ui(c,d,2e+1), Ui(c,d,2e+2), J(c,d,e+1), K(c,d,e+1), L(c,d,e+1), and M(c,d,e+1); and 4 outputs Bo(c,d,2e+1), Bo(c,d,2e+2), Fo(c,d,2e+1), and Fo(c,d,2e+2). The stage (slice “c”, ring “d”, stage “e”) also consists of four 4:1 Muxes namely F(c,d,2e+1), F(c,d,2e+2), B(c,d,2e+1), and B(c,d,2e+2). The 4:1 Mux F(c,d,2e+1) has four inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), Ui(c,d,2e+2), and J(c,d,e+1), and has one output Fo(c,d,2e+1). The 4:1 Mux F(c,d,2e+2) has four inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), Ui(c,d,2e+1), and K(c,d,e+1), and has one output Fo(c,d,2e+2).

The 4:1 Mux B(c,d,2e+1) has four inputs namely Ui(c,d,2e+1), Ui(c,d,2e+2), Ri(c,d,2e+2), and L(c,d,e+1), and has one output Bo(c,d,2e+1). The 4:1 Mux B(c,d,2e+2) has four inputs namely Ui(c,d,2e+1), Ui(c,d,2e+2), Ri(c,d,2e+1) and M(c,d,e+1), and has one output Bo(c,d,2e+2). In different embodiments the inputs J(c,d,e+1), K(c,d,e+1), L(c,d,e+1), and M(c,d,e+1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (slice “c”, ring “d”, stage “e+1”) consists of 8 inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+3), Ui(c,d,2e+4), J(c,d,e+2), K(c,d,e+2), L(c,d,e+2), and M(c,d,e+2); and 4 outputs Bo(c,d,2e+3), Bo(c,d,2e+4), Fo(c,d,2e+3), and Fo(c,d,2e+4). The stage (slice “c”, ring “d”, stage “e+1”) also consists of four 4:1 Muxes namely F(c,d,2e+3), F(c,d,2e+4), B(c,d,2e+3), and B(c,d,2e+4). The 4:1 Mux F(c,d,2e+3) has four inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+4), and J(c,d,e+2), and has one output Fo(c,d,2e+3). The 4:1 Mux F(c,d,2e+4) has four inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+3), and K(c,d,e+2), and has one output Fo(c,d,2e+4).

The 4:1 Mux B(c,d,2e+3) has four inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4), Ri(c,d,2e+4), and L(c,d,e+2), and has one output Bo(c,d,2e+3). The 4:1 Mux B(c,d,2e+4) has four inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4), Ri(c,d,2e+3) and M(c,d,e+2), and has one output Bo(c,d,2e+4). In different embodiments the inputs J(c,d,e+2), K(c,d,e+2), L(c,d,e+2), and M(c,d,e+2) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The output Fo(c,d,2e+1) of the stage (slice “c”, ring “d”, stage “e”) is connected to the input Ri(c,d,2e+3) of the stage (slice “c”, ring “d”, stage “e+1”) which is called hereinafter an internal connection between two successive stages of a ring. And the output Bo(c,d,2e+3) of the stage (slice “c”, ring “d”, stage “e+1”) is connected to the input Ui(c,d,2e+1) of the stage (slice “c”, ring “d”, stage “e”), is another internal connection between stage “e” and stage “e+1” of the ring (slice “c”, ring “d”).

Referring to diagram 100C6 in FIG. 1C6 illustrates specific details of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C in FIG. 1C, particularly the internal connections between two successive stages of any ring of a slice, in one embodiment. The stage (slice “c”, ring “d”, stage “e”) consists of 4 inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), Ui(c,d,2e+1), and Ui(c,d,2e+2); and 4 outputs Bo(c,d,2e+1), Bo(c,d,2e+2), Fo(c,d,2e+1), and Fo(c,d,2e+2). The stage (slice “c”, ring “d”, stage “e”) also consists of four 3:1 Muxes namely F(c,d,2e+1), F(c,d,2e+2), and B(c,d,2e+1), and B(c,d,2e+2). The 3:1 Mux F(c,d,2e+1) has three inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), and Ui(c,d,2e+2), and has one output Fo(c,d,2e+1). The 3:1 Mux F(c,d,2e+2) has three inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), and Ui(c,d,2e+1), and has one output Fo(c,d,2e+2).

The 3:1 Mux B(c,d,2e+1) has three inputs namely Ui(c,d,2e+1), Ui(c,d,2e+2), and Ri(c,d,2e+2), and has one output Bo(c,d,2e+1). The 3:1 Mux B(c,d,2e+2) has three inputs namely Ui(c,d,2e+1), Ui(c,d,2e+2), and Ri(c,d,2e+1), and has one output Bo(c,d,2e+2).

The stage (slice “c”, ring “d”, stage “e+1”) consists of 4 inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+3), and Ui(c,d,2e+4); and 4 outputs Bo(c,d,2e+3), Bo(c,d,2e+4), Fo(c,d,2e+3), and Fo(c,d,2e+4). The stage (slice “c”, ring “d”, stage “e+1”) also consists of four 3:1 Muxes namely F(c,d,2e+3), F(c,d,2e+4), B(c,d,2e+3), and B(c,d,2e+4). The 3:1 Mux F(c,d,2e+3) has three inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), and Ui(c,d,2e+4), and has one output Fo(c,d,2e+3). The 3:1 Mux F(c,d,2e+4) has three inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), and Ui(c,d,2e+3), and has one output Fo(c,d,2e+4).

The 3:1 Mux B(c,d,2e+3) has three inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4), and Ri(c,d,2e+4), and has one output Bo(c,d,2e+3). The 3:1 Mux B(c,d,2e+4) has three inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4), and Ri(c,d,2e+3), and has one output Bo(c,d,2e+4).

The output Fo(c,d,2e+1) of the stage (slice “c”, ring “d”, stage “e”) is connected to the input Ri(c,d,2e+3) of the stage (slice “c”, ring “d”, stage “e+1”) which is called hereinafter an internal connection between two successive stages of a ring. And the output Bo(c,d,2e+3) of the stage (slice “c”, ring “d”, stage “e+1”) is connected to the input Ui(c,d,2e+1) of the stage (slice “c”, ring “d”, stage “e”), is another internal connection between stage “e” and stage “e+1” of the ring (slice “c”, ring “d”).

Just the same way the two successive stages (slice “c’, ring “d”, stage “e”) and (slice ‘c”, ring “d”, stage “e+1”) have internal connections between them as described in diagrams 100C5 of FIG. 1C5 and 100C6 of FIG. 1C6 in two different embodiments, any two successive stages have similar internal connections for any values of “c”, “d”, “e” of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C in FIG. 1C belonging to any block of the two dimensional grid 800 in FIG. 8, in some embodiments. For example stage (slice 1, ring 1, stage 0) and stage (slice 1, ring 1, stage 1) have similar internal connections; and stage (slice 1, ring 1, stage “m−1”) and stage (slice 1, ring 1, stage “m”) have similar internal connections.

Stage (slice 1, ring 1, stage 0) is also called hereinafter the “entry stage” or “first stage” of (slice 1, ring 1), since inlet links and outlet links of the computational block are directly connected to stage (slice 1, ring 1, stage 0). Also stage (slice 1, ring 1, stage “m”) is hereinafter the “last stage” or “root stage” of (slice 1, ring 1).

The stage (slice 1, ring 2, stage 0) consists of 8 inputs namely Ri(1,2,1), Ri(1,2,2), Ui(1,2,1), Ui(1,2,2), J(1,2,1), K(1,2,1), L(1,2,1), and M(1,2,1); and 4 outputs Bo(1,2,1), Bo(1,2,2), Fo(1,2,1), and Fo(1,2,2). The stage (slice 1, ring “2”, stage “0”) also consists of four 4:1 Muxes namely F(1,2,1), F(1,2,2), B(1,2,1), and B(1,2,2). The 4:1 Mux F(1,2,1) has four inputs namely Ri(1,2,1), Ri(1,2,2), Ui(1,2,2), and J(1,2,1), and has one output Fo(1,2,1). The 4:1 Mux F(1,2,2) has four inputs namely Ri(1,2,1), Ri(1,2,2), Ui(1,2,1), and K(1,2,1), and has one output Fo(1,2,2).

The 4:1 Mux B(1,2,1) has four inputs namely Ui(1,2,1), Ui(1,2,2), Ri(1,2,2), and L(1,2,1), and has one output Bo(1,2,1). The 4:1 Mux B(1,2,2) has four inputs namely Ui(1,2,1), Ui(1,2,2), Ri(1,2,1) and M(1,2,1), and has one output Bo(1,2,2). In different embodiments the inputs J(1,2,1), K(1,2,1), L(1,2,1), and M(1,2,1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (slice 1, ring 2, stage “n”) consists of 8 inputs namely Ri(1,2,2n+1), Ri(1,2,2n+2), Ui(1,2,2n+1), Ui(1,2,2n+2), J(1,2,n+1), K(1,2,n+1), L(1,2,n+1), and M(1,2,n+1); and 4 outputs Bo(1,2,2n+1), Bo(1,2,2n+2), Fo(1,2,2n+1), and Fo(1,2,2n+2). The stage (slice 1, ring 2, stage “n”) also consists of four 4:1 Muxes namely F(1,2,2n+1), F(1,2,2n+2), B(1,2,2n+1), and B(1,2,2n+2). The 4:1 Mux F(1,2,2n+1) has four inputs namely Ri(1,2,2n+1), Ri(1,2,2n+2), Ui(1,2,2n+2), and J(1,2,n+1), and has one output Fo(1,2,2n+1). The 4:1 Mux F(1,2,2n+2) has four inputs namely Ri(1,2,2n+1), Ri(1,2,2n+2), Ui(1,2,2n+1), and K(1,2,n+1), and has one output Fo(1,2,2n+2).

The 4:1 Mux B(1,2,2n+1) has four inputs namely Ui(1,2,n+1), Ui(1,2,2n+2), Ri(1,2,2n+2), and L(1,2,n+1), and has one output Bo(1,2,2n+1). The 4:1 Mux B(1,2,2n+2) has four inputs namely Ui(1,2,2n+1), Ui(1,2,2n+2), Ri(1,2,2n+1) and M(1,2,n+1), and has one output Bo(1,2,2n+2). In different embodiments the inputs J(1,2,n+1), K(1,2,n+1), L(1,2,n+1), and M(1,2,n+1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

Just the same way the stage (slice 1, ring 2, stage 0), there are also stages (slice 1, ring 2, stage 1), (slice 1, ring 2, stage 2), (slice 1, ring 2, stage 3), . . . (slice 1, ring 2, stage “n−1”), (slice 1, ring 2, stage “n”) in that order, where the stages from (slice 1, ring 2, stage 1), (slice 1, ring 2, stage 2), . . . , (slice 1, ring 2, stage “n−1”) are not shown in the diagram 100C.

The stage (slice 2, ring 1, stage 0) consists of 8 inputs namely Ri(2,1,1), Ri(2,1,2), Ui(2,1,1), Ui(2,1,2), J(2,1,1), K(2,1,1), L(2,1,1), and M(2,1,1); and 4 outputs Bo(2,1,1), Bo(2,1,2), Fo(2,1,1), and Fo(2,1,2). The stage (slice 2, ring “1”, stage “0”) also consists of four 4:1 Muxes namely F(2,1,1), F(2,1,2), B(2,1,1), and B(2,1,2). The 4:1 Mux F(2,1,1) has four inputs namely Ri(2,1,1), Ri(2,1,2), Ui(2,1,2), and J(2,1,1), and has one output Fo(2,1,1). The 4:1 Mux F(2,1,2) has four inputs namely Ri(2,1,1), Ri(2,1,2), Ui(2,1,1), and K(2,1,1), and has one output Fo(2,1,2).

The 4:1 Mux B(2,1,1) has four inputs namely Ui(2,1,1), Ui(2,1,2), Ri(2,1,2), and L(2,1,1), and has one output Bo(2,1,1). The 4:1 Mux B(2,1,2) has four inputs namely Ui(2,1,1), Ui(2,1,2), Ri(2,1,1) and M(2,1,1), and has one output Bo(2,1,2). In different embodiments the inputs J(2,1,1), K(2,1,1), L(2,1,1), and M(2,1,1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (slice 2, ring 1, stage “x”) consists of 8 inputs namely Ri(2,1,2x+1), Ri(2,1,2x+2), Ui(2,1,2x+1), Ui(2,1,2x+2), J(2,1,x+1), K(2,1,x+1), L(2,1,x+1), and M(2,1,x+1); and 4 outputs Bo(2,1,2x+1), Bo(2,1,2x+2), Fo(2,1,2x+1), and Fo(2,1,2x+2). The stage (slice 2, ring 1, stage “x”) also consists of four 4:1 Muxes namely F(2,1,2x+1), F(2,1,2x+2), B(2,1,2x+1), and B(2,1,2x+2). The 4:1 Mux F(2,1,2x+1) has four inputs namely Ri(2,1,2x+1), Ri(2,1,2x+2), Ui(2,1,2x+2), and J(2,1,x+1), and has one output Fo(2,1,2x+1). The 4:1 Mux F(2,1,2x+2) has four inputs namely Ri(2,1,2x+1), Ri(2,1,2x+2), Ui(2,1,2x+1), and K(2,1,x+1), and has one output Fo(2,1,2x+2).

The 4:1 Mux B(2,1,2x+1) has four inputs namely Ui(2,1,2x+1), Ui(2,1,2x+2), Ri(2,1,2x+2), and L(2,1,x+1), and has one output Bo(2,1,2x+1). The 4:1 Mux B(2,1,2x+2) has four inputs namely Ui(2,1,2x+1), Ui(2,1,2x+2), Ri(2,1,2x+1) and M(2,1,x+1), and has one output Bo(2,1,2x+2). In different embodiments the inputs J(2,1,x+1), K(2,1,x+1), L(2,1,x+1), and M(2,1,x+1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

Just the same way the stage (slice 2, ring 1, stage 0), there are also stages (slice 2, ring 1, stage 1), (slice 2, ring 1, stage 2), (slice 2, ring 1, stage 3), . . . (slice 2, ring 1, stage “m−1”), (slice 2, ring 1, stage “x”) in that order, where the stages from (slice 2, ring 1, stage 1), (slice 2, ring 1, stage 2), . . . , (slice 2, ring 1, stage “x−1”) are not shown in the diagram 100C.

The stage (slice 2, ring 2, stage 0) consists of 8 inputs namely Ri(2,2,1), Ri(2,2,2), Ui(2,2,1), Ui(2,2,2), J(2,2,1), K(2,2,1), L(2,2,1), and M(2,2,1); and 4 outputs Bo(2,2,1), Bo(2,2,2), Fo(2,2,1), and Fo(2,2,2). The stage (slice 2, ring “2”, stage “0”) also consists of four 4:1 Muxes namely F(2,2,1), F(2,2,2), B(2,2,1), and B(2,2,2). The 4:1 Mux F(2,2,1) has four inputs namely Ri(2,2,1), Ri(2,2,2), Ui(2,2,2), and J(2,2,1), and has one output Fo(2,2,1). The 4:1 Mux F(2,2,2) has four inputs namely Ri(2,2,1), Ri(2,2,2), Ui(2,2,1), and K(2,2,1), and has one output Fo(2,2,2).

The 4:1 Mux B(2,2,1) has four inputs namely Ui(2,2,1), Ui(2,2,2), Ri(2,2,2), and L(2,2,1), and has one output Bo(2,2,1). The 4:1 Mux B(2,2,2) has four inputs namely Ui(2,2,1), Ui(2,2,2), Ri(2,2,1) and M(2,2,1), and has one output Bo(2,2,2). In different embodiments the inputs J(2,2,1), K(2,2,1), L(2,2,1), and M(2,2,1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (slice 2, ring 2, stage “x”) consists of 8 inputs namely Ri(2,2,2x+1), Ri(2,2,2x+2), Ui(2,2,2x+1), Ui(2,2,2x+2), J(2,2,x+1), K(2,2,x+1), L(2,2,x+1), and M(2,2,x+1); and 4 outputs Bo(2,2,2x+1), Bo(2,2,2x+2), Fo(2,2,2x+1), and Fo(2,2,2x+2). The stage (slice 2, ring 2, stage “y”) also consists of four 4:1 Muxes namely F(2,2,2y+1), F(2,2,2y+2), B(2,2,2y+1), and B(2,2,2y+2). The 4:1 Mux F(2,2,2y+1) has four inputs namely Ri(2,2,2y+1), Ri(2,2,2y+2), Ui(2,2,2y+2), and J(2,2,y+1), and has one output Fo(2,2,2y+1). The 4:1 Mux F(2,2,2y+2) has four inputs namely Ri(2,2,2y+1), Ri(2,2,2y+2), Ui(2,2,2y+1), and K(2,2,y+1), and has one output Fo(2,2,2y+2).

The 4:1 Mux B(2,2,2y+1) has four inputs namely Ui(2,2,2y+1), Ui(2,2,2y+2), Ri(2,2,2y+2), and L(2,2,y+1), and has one output Bo(2,2,2y+1). The 4:1 Mux B(2,2,2y+2) has four inputs namely Ui(2,2,2y+1), Ui(2,2,2y+2), Ri(2,2,2y+1) and M(2,2,y+1), and has one output Bo(2,2,2y+2). In different embodiments the inputs J(2,2,y+1), K(2,2,y+1), L(2,2,y+1), and M(2,2,y+1) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

Just the same way the stage (slice 2, ring 2, stage 0), there are also stages (slice 2, ring 2, stage 1), (slice 2, ring 2, stage 2), (slice 2, ring 2, stage 3), . . . (slice 2, ring 2, stage “y−1”), (slice 2, ring 2, stage “y”) in that order, where the stages from (slice 2, ring 2, stage 1), (slice 2, ring 2, stage 2), . . . , (slice 2, ring 2, stage “y−1”) are not shown in the diagram 100C.

As illustrated in diagrams 100C5 in FIG. 1C5 and 100C6 in FIG. 1C6, the similar internal connections between two successive stages of any ring of any slice of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C in FIG. 1C, in some embodiments are provided for all the slices c=1, 2; for all the rings in each of the slices d=1, 2; and for all the stages namely when c=1, d=1, e=[1,m]; when c=1, d=2, e=[1,n]; when c=2, d=1, e=[1,x]; and when c=2, d=2; e=[1,y].

Each stage of any ring of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C consists of 4 inputs and 4 outputs. Even though each stage has four 4:1 muxes, in other embodiments any of these stages can be one of the four by four switch diagrams namely 200A of FIG. 2A, 200B of FIG. 2B, 200C of FIG. 2C, 200D of FIG. 2D, 200G of FIG. 2G, 200H of FIG. 2H, 200I of FIG. 2I, 200J of FIG. 2J, or one of the eight by four switch diagrams namely 200E of FIG. 2E, 200F of FIG. 2F, or fourteen by six switch diagram 200K of FIG. 2K, or six by six switch diagram 200L of FIG. 2L, or eight by six switch diagram 200M of FIG. 2M, or twelve by six switch diagram 200N of FIG. 2N.

In general, any ring of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) illustrated in 100C also may have inputs and outputs connected from computational block from either only from left-hand side as in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A; or only from right-hand side; or from both left-hand and right-hand sides as in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B.

Applicant now notes a few aspects of the diagram 100C in FIG. 1C an exemplary partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to one computational block, with each computational block having 16 inlet links and 4 outlet links as follows: (Also these aspects are helpful in more optimization of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) as well as faster scheduling of the connections between outlet links of the computational blocks and the inlet links of the computational blocks.)

1) The partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C in FIG. 1C is divided into two slices namely slice 1 and slice 2. The outlet links of the computational block namely O1 and O2 are connected to only one slice i.e. slice 1. In other words outlet links O1 and O2 are absolutely not connected to slice 2. Similarly the outlet links of the computational block namely O3 and O4 are connected to only one slice i.e. slice 2. In other words outlet links O3 and O4 are absolutely not connected to slice 1. 2) The second aspect is all the hop wires and multi-drop hop wires originating from slice 1 from any block will be terminating only in the slice 1 of any other block. Similarly all the hop wires and multi-drop hop wires originating from slice 2 from any block will be terminating only in the slice 2 of any other block. 3) The third aspect is the mux whose output is directly connected to each inlet link of the computational block must have at least one input connected from each slice of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C. That is for example since the 4:1 mux B(1,1,1), belonging to slice 1, and having its output Bo(1,1,1) directly connected to inlet link I1 must have at least one of its inputs connecting from an output of a mux of a stage of a ring of slice 2 as well. This property must be satisfied for all the inlet links of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C.

Referring to diagram 100C1 in FIG. 1C1, diagram 100C2 in FIG. 1C2, diagram 100C3 in FIG. 1C3, and diagram 100C4 in FIG. 1C4 illustrate the details of the foregoing third aspect of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C of FIG. 1C. Applicant notes that diagram 100C1 in FIG. 1C1, diagram 100C2 in FIG. 1C2, diagram 100C3 in FIG. 1C3, and diagram 100C4 in FIG. 1C4 are all actually part of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C of FIG. 1C and these separate diagrams are necessary only to avoid the clutter in the diagram 100C of FIG. 1C.

The connections illustrated between different slices in diagram 100C1 in FIG. 1C1, diagram 100C2 in FIG. 1C2, diagram 100C3 in FIG. 1C3, and diagram 100C4 in FIG. 1C4 are the only connections between different slices, in some exemplary embodiments. In general the connections between different slices are given only at the terminating muxes i.e. whose outputs are directly connected to one of the inlet links of the computational block.

Referring to diagram 100C1 in FIG. 1C1 illustrate the connections between the stage (slice 1, ring 1, stage 0) and between the stage (slice 2, ring 1, stage 0). The same connection that is given to the input Ui(1,1,1) is also connected to the input L(2,1,1). The same connection that is given to the input Ui(1,1,2) is also connected to the input M(2,1,1). Similarly the same connection that is given to the input Ui(2,1,1) is also connected to the input L(1,1,1). The same connection that is given to the input Ui(2,1,2) is also connected to the input M(1,1,1).

Therefore inlet link I1 can be essentially connected through the 4:1 mux B(1,1,1) with three of its inputs connecting from slice 1 namely Ui(1,1,1), Ui(1,1,2), Ri(1,1,2) and one input L(1,1,1) connecting from slice 2. The inlet link I2 can be essentially connected through the 4:1 mux B(1,1,2) with three of its inputs connecting from slice 1 namely Ui(1,1,1), Ui(1,1,2), Ri(1,1,1) and one input M(1,1,1) connecting from slice 2. The inlet link I9 can be essentially connected through the 4:1 mux B(1,2,1) with three of its inputs connecting from slice 2 namely Ui(2,1,1), Ui(2,1,2), Ri(2,1,2) and one input L(2,1,1) connecting from slice 1. The inlet link I10 can be essentially connected through the 4:1 mux B(2,1,2) with three of its inputs connecting from slice 2 namely Ui(2,1,1), Ui(2,1,2), Ri(2,1,1) and one input M(2,1,1) connecting from slice 1. Hence all the inlet links I1, I2, I9 and I10 are all independently reachable from both slice 1 and slice 2.

Referring to diagram 100C2 in FIG. 1C2 illustrate the connections between the stage (slice 1, ring 2, stage 0) and between the stage (slice 2, ring 2, stage 0). The same connection that is given to the input Ui(1,2,1) is also connected to the input M(2,2,1). The same connection that is given to the input Ui(1,2,2) is also connected to the input L(2,2,1). Similarly the same connection that is given to the input Ui(2,2,1) is also connected to the input M(1,2,1). The same connection that is given to the input Ui(2,2,2) is also connected to the input L(1,2,1).

Therefore inlet link I3 can be essentially connected through the 4:1 mux B(1,2,1) with three of its inputs connecting from slice 1 namely Ui(1,2,1), Ui(1,2,2), Ri(1,2,2) and one input M(2,2,1) connecting from slice 2. The inlet link I4 can be essentially connected through the 4:1 mux B(1,2,2) with three of its inputs connecting from slice 1 namely Ui(1,2,1), Ui(1,2,2), Ri(1,2,1) and one input M(1,2,1) connecting from slice 2. The inlet link I11 can be essentially connected through the 4:1 mux B(2,2,1) with three of its inputs connecting from slice 2 namely Ui(2,2,1), Ui(2,2,2), Ri(2,2,2) and one input L(2,2,1) connecting from slice 1. The inlet link I12 can be essentially connected through the 4:1 mux B(2,2,2) with three of its inputs connecting from slice 2 namely Ui(2,2,1), Ui(2,2,2), Ri(2,2,1) and one input M(2,2,1) connecting from slice 1. Hence all the inlet links I3, I4, I11 and I12 are all independently reachable from both slice 1 and slice 2.

Referring to diagram 100C3 in FIG. 1C3 illustrate the connections between the stage (slice 1, ring 1, stage “m”) and between the stage (slice 2, ring 2, stage “y”). The same connection that is given to the input Ri(1,1,2m+1) is also connected to the input J(2,2,y+1). The same connection that is given to the input Ri(1,1,2m+2) is also connected to the input K(2,2,y+1). Similarly the same connection that is given to the input Ri(2,2,2y+1) is also connected to the input J(1,1,m+1). The same connection that is given to the input Ri(2,2,2y+2) is also connected to the input K(1,1,m+1).

Therefore inlet link I5 can be essentially connected through the 4:1 mux F(1,1,2m+1) with three of its inputs connecting from slice 1 namely Ri(1,1,2m+1), Ri(1,1,2m+2), Ui(1,1,2m+2) and one input J(1,1,m+1) connecting from slice 2. The inlet link I6 can be essentially connected through the 4:1 mux F(1,1,2m+2) with three of its inputs connecting from slice 1 namely Ri(1,1,2m+1), Ri(1,1,2m+2),Ui(1,1,2m+1) and one input K(1,1,m+1) connecting from slice 2. The inlet link I15 can be essentially connected through the 4:1 mux F(2,2,2y+1) with three of its inputs connecting from slice 2 namely Ri(2,2,2y+1), Ri(2,2,2y+2), Ui(2,2,2y+2) and one input J(2,2,y+1) connecting from slice 1. The inlet link I16 can be essentially connected through the 4:1 mux F(2,2,2y+2) with three of its inputs connecting from slice 2 namely Ri(2,2,2y+1), Ri(2,2,2y+2), Ui(2,2,2y+1) and one input K(2,2,y+1) connecting from slice 1. Hence all the inlet links I5, I6, I15 and I16 are all independently reachable from both slice 1 and slice 2.

Referring to diagram 100C4 in FIG. 1C4 illustrate the connections between the stage (slice 1, ring 2, stage “n”) and between the stage (slice 2, ring 1, stage “x”). The same connection that is given to the input Ri(1,2,2n+1) is also connected to the input K(2,1,x+1). The same connection that is given to the input Ri(1,2,2n+2) is also connected to the input J(2,1,x+1). Similarly the same connection that is given to the input Ri(2,1,2x+1) is also connected to the input K(1,2,n+1). The same connection that is given to the input Ri(2,1,2x+2) is also connected to the input J(1,2,n+1).

Therefore inlet link I7 can be essentially connected through the 4:1 mux F(1,2,2n+1) with three of its inputs connecting from slice 1 namely Ri(1,2,2n+1), Ri(1,2,2n+2), Ui(1,2,2n+2) and one input J(1,2,n+1) connecting from slice 2. The inlet link I8 can be essentially connected through the 4:1 mux F(1,2,2n+2) with three of its inputs connecting from slice 1 namely Ri(1,2,2n+1), Ri(1,2,2n+2),Ui(1,2,2n+1) and one input K(1,2,n+1) connecting from slice 2. The inlet link I13 can be essentially connected through the 4:1 mux F(2,1,2x+1) with three of its inputs connecting from slice 2 namely Ri(2,1,2x+1), Ri(2,1,2x+2), Ui(2,1,2x+2) and one input J(2,1,x+1) connecting from slice 1. The inlet link I14 can be essentially connected through the 4:1 mux F(2,1,2x+2) with three of its inputs connecting from slice 2 namely Ri(2,1,2x+1), Ri(2,1,2x+2), Ui(2,1,2x+1) and one input K(2,1,x+1) connecting from slice 1. Hence all the inlet links I7, I8, I13 and I14 are all independently reachable from both slice 1 and slice 2.

The connections illustrated between different slices, in several embodiments, in diagram 100C1 in FIG. 1C1, diagram 100C2 in FIG. 1C2, diagram 100C3 in FIG. 1C3, and diagram 100C4 in FIG. 1C4 are the only connections between different slices. And also the terminating muxes i.e. whose outputs are directly connected to one of the inlet links of the computational block have three inputs coming from one slice and one input coming from another slice. In other embodiments it is also possible so that the terminating muxes i.e. whose outputs are directly connected to one of the inlet links of the computational block have two inputs coming from one slice and two inputs coming from another slice.

Also in general the number of slices in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C of FIG. 1C may be more than or equal to one. In such a case terminating muxes i.e. whose outputs are directly connected to one of the inlet links of the computational block will have at least one input coming from each slice. And the outlet links of the computational block will be divided and connected to each slice; however each outlet link of the computational block will be connected to only one slice. Also in general the hop wires and multi-drop hop wires are connected to only between the corresponding slices of different blocks, in some embodiments some of the hop wires and multi-drop hop wires may be connected between different slices of different blocks even if it is done partially.

Referring to diagram 100D in FIG. 1D, in one embodiment, an exemplary slice of a partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where N₁, N₂, d and s are positive integers corresponding to one computational block. (In an embodiment where there is only one slice the diagram 100D in FIG. 1D is a partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to one computational block). The Slice in diagram 100D in FIG. 1D consists of two rings namely “ring 1” and “ring 2”.

The ring “ring 1” consists of “m+1” stages namely (ring 1, stage 0), (ring 1, stage 1), . . . (ring 1, stage “m−1”), and (ring 1, stage “m”). And the ring “ring 2” consists of “n+1” stages namely (ring 2, stage 0), (ring 2, stage 1), . . . (ring 2, stage “n−1”), and (ring 2, stage “n”), where “m” and “n” are positive integers.

Ring “ring 1” has inlet links Ri(1,1,1) and Ri(1,1,2) from the left-hand side, and has outlet links Bo(1,1,1) and Bo(1,1,2) from left-hand side. Ring (“ring 1” also has inlet links Ui(1,1,2m+1) and Ui(1,1,2m+2) from the right-hand side, and has outlet links Fo(1,1,2m+1) and Fo(1,1,2m+2) from right-hand side. Ring “ring 2” has inlet links Ri(1,2,1) and Ri(1,2,2) from left-hand side, and outlet links Bo(1,2,1) and Bo(1,2,2) from left-hand side. Ring “ring 2” also has inlet links Ui(1,2,2n+1) and Ui(1,2,2n+2) from the right-hand side, and has outlet links Fo(1,2,2n+1) and Fo(1,2,2n+2) from right-hand side.

Referring to two dimensional grid 800 in FIG. 8 illustrates, in another embodiment, each block of 2D-grid 800 consists of one or more slices of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D with a plurality of inlet links and a plurality of outlet links. Also the 2D-grid 800 is organized in the fourth quadrant of the 2D-Plane. In other embodiments the 2D-grid 800 may be organized as either first quadrant, or second quadrant or third quadrant of the 2D-Plane.

Referring to a slice of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D in FIG. 1D, the stage (ring 1, stage 0) consists of 8 inputs namely Ri(1,1), Ri(1,2), Ui(1,1), Ui(1,2), J(1,1), K(1,1), L(1,1), and M(1,1); and 4 outputs Bo(1,1), Bo(1,2), Fo(1,1), and Fo(1,2). The stage (ring “1”, stage “0”) also consists of four 4:1 Muxes namely F(1,1), F(1,2), B(1,1), and B(1,2). The 4:1 Mux F(1,1) has four inputs namely Ri(1,1), Ri(1,2), Ui(1,2), and J(1,1), and has one output Fo(1,1). The 4:1 Mux F(1,2) has four inputs namely Ri(1,1), Ri(1,2), Ui(1,1), and K(1,1), and has one output Fo(1,2).

The 4:1 Mux B(1,1) has four inputs namely Ui(1,1), Ui(1,2), Ri(1,2), and L(1,1), and has one output Bo(1,1). The 4:1 Mux B(1,2) has four inputs namely Ui(1,1), Ui(1,2), Ri(1,1) and M(1,1), and has one output Bo(1,2). In different embodiments the inputs J(1,1), K(1,1), L(1,1), and M(1,1) are connected from any of the outputs of any other stages of any ring of any slice of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring 1, stage “m”) consists of 8 inputs namely Ri(1,2m+1), Ri(1,2m+2), Ui(1,2m+1), Ui(1,2m+2), J(1,m+1), K(1,m+1), L(1,m+1), and M(1,m+1); and 4 outputs Bo(1,2m+1), Bo(1,2m+2), Fo(1,2m+1), and Fo(1,2m+2). The stage (ring 1, stage “m”) also consists of four 4:1 Muxes namely F(1,2m+1), F(1,2m+2), B(1,2m+1), and B(1,2m+2). The 4:1 Mux F(1,2m+1) has four inputs namely Ri(1,2m+1), Ri(1,2m+2), Ui(1,2m+2), and J(1,m+1), and has one output Fo(1,2m+1). The 4:1 Mux F(1,2m+2) has four inputs namely Ri(1,2m+1), Ri(1,2m+2), Ui(1,2m+1), and K(1,m+1), and has one output Fo(1,2m+2).

The 4:1 Mux B(1,2m+1) has four inputs namely Ui(1,2m+1), Ui(1,2m+2), Ri(1,2m+2), and L(1,m+1), and has one output Bo(1,2m+1). The 4:1 Mux B(1,2m+2) has four inputs namely Ui(1,2m+1), Ui(1,2m+2), Ri(1,2m+1) and M(1,m+1), and has one output Bo(1,2m+2). In different embodiments the inputs J(1,m+1), K(1,m+1), L(1,m+1), and M(1,m+1) are connected from any of the outputs of any other stages of any ring of any slice of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Just the same way the stage (ring 1, stage 0), there are also stages (ring 1, stage 1), (ring 1, stage 2), (ring 1, stage 3), . . . (ring 1, stage “m−1”), (ring 1, stage “m”) in that order.

Referring to diagram 100C5 in FIG. 1C5 illustrates specific details of the slice of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D in FIG. 1D, particularly the internal connections between two successive stages of any ring of a slice, in one embodiment. The stage (slice “c”, ring “d”, stage “e”) consists of 8 inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), Ui(c,d,2e+1), Ui(c,d,2e+2), J(c,d,e+1), K(c,d,e+1), L(c,d,e+1), and M(c,d,e+1); and 4 outputs Bo(c,d,2e+1), Bo(c,d,2e+2), Fo(c,d,2e+1), and Fo(c,d,2e+2). The stage (slice “c”, ring “d”, stage “e”) also consists of four 4:1 Muxes namely F(c,d,2e+1), F(c,d,2e+2), B(c,d,2e+1), and B(c,d,2e+2). The 4:1 Mux F(c,d,2e+1) has four inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), Ui(c,d,2e+2), and J(c,d,e+1), and has one output Fo(c,d,2e+1). The 4:1 Mux F(c,d,2e+2) has four inputs namely Ri(c,d,2e+1), Ri(c,d,2e+2), Ui(c,d,2e+1), and K(c,d,e+1), and has one output Fo(c,d,2e+2).

The 4:1 Mux B(c,d,2e+1) has four inputs namely Ui(c,d,2e+1), Ui(c,d,2e+2), Ri(c,d,2e+2), and L(c,d,e+1), and has one output Bo(c,d,2e+1). The 4:1 Mux B(c,d,2e+2) has four inputs namely Ui(c,d,2e+1), Ui(c,d,2e+2), Ri(c,d,2e+1) and M(c,d,e+1), and has one output Bo(c,d,2e+2). In different embodiments the inputs J(c,d,e+1), K(c,d,e+1), L(c,d,e+1), and M(c,d,e+1) are connected from any of the outputs of any other stages of any ring of any slice of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (slice “c”, ring “d”, stage “e+1”) consists of 8 inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+3), Ui(c,d,2e+4), J(c,d,e+2), K(c,d,e+2), L(c,d,e+2), and M(c,d,e+2); and 4 outputs Bo(c,d,2e+3), Bo(c,d,2e+4), Fo(c,d,2e+3), and Fo(c,d,2e+4). The stage (slice “c”, ring “d”, stage “e+1”) also consists of four 4:1 Muxes namely F(c,d,2e+3), F(c,d,2e+4), B(c,d,2e+3), and B(c,d,2e+4). The 4:1 Mux F(c,d,2e+3) has four inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+4), and J(c,d,e+2), and has one output Fo(c,d,2e+3). The 4:1 Mux F(c,d,2e+4) has four inputs namely Ri(c,d,2e+3), Ri(c,d,2e+4), Ui(c,d,2e+3), and K(c,d,e+2), and has one output Fo(c,d,2e+4).

The 4:1 Mux B(c,d,2e+3) has four inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4), Ri(c,d,2e+4), and L(c,d,e+2), and has one output Bo(c,d,2e+3). The 4:1 Mux B(c,d,2e+4) has four inputs namely Ui(c,d,2e+3), Ui(c,d,2e+4), Ri(c,d,2e+3) and M(c,d,e+2), and has one output Bo(c,d,2e+4). In different embodiments the inputs J(c,d,e+2), K(c,d,e+2), L(c,d,e+2), and M(c,d,e+2) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The output Fo(c,d,2e+1) of the stage (slice “c”, ring “d”, stage “e”) is connected to the input Ri(c,d,2e+3) of the stage (slice “c”, ring “d”, stage “e+1”) which is called hereinafter an internal connection between two successive stages of a ring. And the output Bo(c,d,2e+3) of the stage (slice “c”, ring “d”, stage “e+1”) is connected to the input Ui(c,d,2e+1) of the stage (slice “c”, ring “d”, stage “e”), is another internal connection between stage “e” and stage “e+1” of the ring (slice “c”, ring “d”).

Just the same way the two successive stages (slice “c’, ring “d”, stage “e”) and (slice ‘c”, ring “d”, stage “e+1”) have internal connections between them as described in diagrams 100C5 of FIG. 1C5 in two different embodiments, any two successive stages have similar internal connections for any values of “c”, “d”, “e” of the slice of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D in FIG. 1D belonging to any block of the two dimensional grid 800 in FIG. 8, in some embodiments. For example stage (slice 1, ring 1, stage 0) and stage (slice 1, ring 1, stage 1) have similar internal connections; and stage (slice 1, ring 1, stage “m−1”) and stage (slice 1, ring 1, stage “m”) have similar internal connections.

The stage (ring 2, stage 0) consists of 8 inputs namely Ri(2,1), Ri(2,2), Ui(2,1), Ui(2,2), J(2,1), K(2,1), L(2,1), and M(2,1); and 4 outputs Bo(2,1), Bo(2,2), Fo(2,1), and Fo(2,2). The stage (ring “2”, stage “0”) also consists of four 4:1 Muxes namely F(2,1), F(2,2), B(2,1), and B(2,2). The 4:1 Mux F(2,1) has four inputs namely Ri(2,1), Ri(2,2), Ui(2,2), and J(2,1), and has one output Fo(2,1). The 4:1 Mux F(2,2) has four inputs namely Ri(2,1), Ri(2,2), Ui(2,1), and K(2,1), and has one output Fo(2,2).

The 4:1 Mux B(2,1) has four inputs namely Ui(2,1), Ui(2,2), Ri(2,2), and L(2,1), and has one output Bo(2,1). The 4:1 Mux B(2,2) has four inputs namely Ui(2,1), Ui(2,2), Ri(2,1) and M(2,1), and has one output Bo(2,2). In different embodiments the inputs J(2,1), K(2,1), L(2,1), and M(2,1) are connected from any of the outputs of any other stages of any ring of any slice of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring 2, stage “n”) consists of 8 inputs namely Ri(2,2n+1), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2), J(2,n+1), K(2,n+1), L(2,n+1), and M(2,n+1); and 4 outputs Bo(2,2n+1), Bo(2,2n+2), Fo(2,2n+1), and Fo(2,2n+2). The stage (ring 2, stage “n”) also consists of four 4:1 Muxes namely F(2,2n+1), F(2,2n+2), B(2,2n+1), and B(2,2n+2). The 4:1 Mux F(2,2n+1) has four inputs namely Ri(2,2n+1), Ri(2,2n+2), Ui(2,2n+2), and J(2,n+1), and has one output Fo(2,2n+1). The 4:1 Mux F(2,2n+2) has four inputs namely Ri(2,2n+1), Ri(2,2n+2), Ui(2,2n+1), and K(2,n+1), and has one output Fo(2,2n+2).

The 4:1 Mux B(2,2n+1) has four inputs namely Ui(2,n+1), Ui(2,2n+2), Ri(2,2n+2), and L(2,n+1), and has one output Bo(2,2n+1). The 4:1 Mux B(2,2n+2) has four inputs namely Ui(2,2n+1), Ui(2,2n+2), Ri(2,2n+1) and M(2,n+1), and has one output Bo(2,2n+2). In different embodiments the inputs J(2,n+1), K(2,n+1), L(2,n+1), and M(2,n+1) are connected from any of the outputs of any other stages of any ring of any slice of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Just the same way the stage (ring 2, stage 0), there are also stages (ring 2, stage 1), (ring 2, stage 2), (ring 2, stage 3), . . . (ring 2, stage “n−1”), (ring 2, stage “n”) in that order.

As illustrated in diagrams 100C5 in FIG. 1C5 the similar internal connections between two successive stages of any ring of any slice of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D in FIG. 1D, in some embodiments are provided for all the slices; for all the rings in each of the slices d=1, 2; and for all the stages namely when d=1, e=[1,m]; when d=2, e=[1,n].

Each stage of any ring of any slice of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D consists of 4 inputs and 4 outputs. Even though each stage has four 4:1 muxes, in other embodiments any of these stages can be one of the four by four switch diagrams namely 200A of FIG. 2A, 200B of FIG. 2B, 200C of FIG. 2C, 200D of FIG. 2D, 200G of FIG. 2G, 200H of FIG. 2H, 200I of FIG. 2I, 200J of FIG. 2J, or one of the eight by four switch diagrams namely 200E of FIG. 2E, 200F of FIG. 2F, or fourteen by six switch diagram 200K of FIG. 2K, or six by six switch diagram 200L of FIG. 2L, or eight by six switch diagram 200M of FIG. 2M, or twelve by six switch diagram 200N of FIG. 2N.

In embodiment I, there are two slices namely Slice 1 and Slice 2 each of them are the diagram 100D in FIG. 1D of a partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). For all the slices incoming links are the incoming links of all stages of all its rings. Similarly for all the slices all outgoing links are outgoing links of all its stages of all its rings. Slice 1's incoming and outgoing links are connected in the following three ways: 1) Some of the Slice 1's outgoing links are directly connected to Slice 1's incoming links. For example they are connected using one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B. 2) Some of the outgoing links of Slice 1 are directly connected to all the inlet links of computational block corresponding to its partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). 3) Some of the incoming links are directly connected from the incoming external hop wires of the corresponding Slice 1 of other blocks 800 of FIG. 8.

Slice 2's incoming and outgoing links are connected in the following three ways: 1) Some of the Slice 2's outgoing links are directly connected to Slice 2's incoming links. For example they are connected using one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B. 2) Some of the incoming links of Slice 2 are directly connected from all the outlet links of computational block corresponding to its partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). 3) Some of the outgoing links are directly connected to the outgoing external hop wires of the corresponding Slice 2 of other blocks 800 of FIG. 8.

In general, any ring of the slice of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) illustrated in 100D may have inputs and outputs directly connected from computational block through any incoming link or outgoing link respectively. Clearly embodiment I, the notion connecting inputs and outputs of the computational block from left-hand side or right-hand side or both sides does not arise, as they are connected through any incoming link or outgoing link.

In embodiment II, there are more than two slices for example namely Slice 1, Slice 2 and Slice 3, (Clearly there may be lot more slices) each of them are the diagram 100D in FIG. 1D of a partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Slice 1's incoming and outgoing links are connected in the following three ways: 1) Some of the Slice 1's outgoing links are directly connected to Slice 1's incoming links. For example they are connected using one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B. 2) Some of the outgoing links of Slice 1 are directly connected to all the inlet links of computational block corresponding to its partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). 3) Some of the incoming links are directly connected from the incoming external hop wires of the corresponding Slice 1 of other blocks 800 of FIG. 8.

Slice 2's incoming and outgoing links are connected in the following three ways: 1) Some of the Slice 2's outgoing links are directly connected to Slice 2's incoming links. For example they are connected using one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B. 2) Some of the incoming links of Slice 2 are directly connected from some or all the outlet links of computational block corresponding to its partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). 3) Some of the outgoing links are directly connected to the outgoing external hop wires of the corresponding Slice 2 of other blocks 800 of FIG. 8.

Slice 3's incoming and outgoing links are connected in the following three ways: 1) Some of the Slice 3's outgoing links are directly connected to Slice 3's incoming links. For example they are connected using one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B. 2) Some of the incoming links of Slice 3 are directly connected from some or all the outlet links of computational block corresponding to its partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). 3) Some of the outgoing links are directly connected to the outgoing external hop wires of the corresponding Slice 3 of other blocks 800 of FIG. 8.

In general, any ring of the slice of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) illustrated in 100D may have inputs and outputs directly connected from computational block through any incoming link or outgoing link respectively. Clearly embodiment II, the notion connecting inputs and outputs of the computational block from left-hand side or right-hand side or both sides does not arise, as they are connected through any incoming link or outgoing link.

In embodiment III, in addition to all the three ways of connections in the above embodiment II, there will be a fourth way of connections, i.e. some of the outgoing links from Slice 2 are connected to incoming links of Slice 3 and vice versa. Similarly there may be connections between any two slices excepting that neither of them is Slice 1.

FIG. 2A illustrates a stage (ring “k”, stage “m”) 200A consists of 4 inputs namely Fi(k,2m+1), Fi(k,2m+2), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of six 2:1 Muxes namely F(k,2m+1), F(k,2m+2) (comprising in combination a forward switch), U(k,2m+1), U(k,2m+2) (comprising in combination a U-turn switch), B(k,2m+1), and B(k,2m+2) (comprising in combination a backward switch). The 2:1 Mux F(k,2m+1) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 2B illustrates a stage (ring “k”, stage “m”) 200B consists of 4 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of eight 2:1 Muxes namely R(k,2m+1), R(k,2m+2) (comprising in combination a Reverse U-turn switch), F(k,2m+1), F(k,2m+2) (comprising in combination a forward switch), U(k,2m+1), U(k,2m+2) (comprising in combination a U-turn switch), B(k,2m+1), and B(k,2m+2) (comprising in combination a backward switch). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 2C illustrates a stage (ring “k”, stage “m”) 200C consists of 4 inputs namely Fi(k,2m+1), Fi(k,2m+2), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Uo(k,2m+1), Uo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of four 2:1 Muxes namely F(k,2m+1), F(k,2m+2) (comprising in combination a forward switch), U(k,2m+1), and U(k,2m+2) (comprising in combination a U-turn switch). The 2:1 Mux F(k,2m+1) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Ui(k,2m+2) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+1) and Ui(k,2m+2) and has one output Uo(k,2m+2).

However the stage “m” of ring “k” with “m+1” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 2 inputs and 2 outputs as shown in diagram 200D in FIG. 2D. FIG. 2D illustrates a stage (ring “k”, stage “m”) 200D consists of 2 inputs namely Fi(k,2m+1) and Fi(k,2m+2); and 2 outputs Fo(k,2m+1) and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of two 2:1 Muxes namely F(k,2m+1), F(k,2m+2) (comprising in combination a forward switch). The 2:1 Mux F(k,2m+1) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2). A stage with 2 inputs and 2 outputs is, in one embodiment, the “last stage” or “root stage” of ring.

The stage “m” of ring “k” with “m+1” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 8 inputs and 4 outputs as shown in diagram 200E in FIG. 2E. FIG. 2E illustrates a stage (ring “k”, stage “m”) 200E consists of 8 inputs namely Fi(k,2m+1), Fi(k,2m+2), Bi(k,2m+1), Bi(k,2m+2), J, K, L, and M; and 4 outputs Uo(k,2m+1), Uo(k,2m+2), Ro(k,2m+1), and Ro(k,2m+2). The stage (ring “k”, stage “m”) also consists of eight 2:1 Muxes namely F(k,2m+1), F(k,2m+2) (comprising in combination a forward switch), R(k,2m+1), R(k,2m+2) (comprising in combination a Reverse U-turn switch), B(k,2m+1), B(k,2m+2) (comprising in combination a backward switch), U(k,2m+1), and U(k,2m+2) (comprising in combination a U-turn switch). The 2:1 Mux R(k,2m+1) has two inputs namely Fi(k,2m+1) and J, and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+2) and K, and has one output Fo(k,2m+2). The 2:1 Mux R(k,2m+1) has two inputs namely Fo(k,2m+1) and Bo(k,2m+2), and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Fo(k,2m+2) and Bo(k,2m+1), and has one output Ro(k,2m+2).

The 2:1 Mux B(k,2m+1) has two inputs namely Bi(k,2m+1) and L, and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Bi(k,2m+2) and M, and has one output Bo(k,2m+2). The 2:1 Mux U(k,2m+1) has two inputs namely Bo(k,2m+1) and Fo(k,2m+2), and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Bo(k,2m+2) and Fo(k,2m+1), and has one output Uo(k,2m+2). In different embodiments the inputs J, K, L, and M are connected from any of the outputs of any other stages of any ring of any block of the multi-stage hierarchical network V_(Comb)(N₁,N₂,d,s).

The diagram 200E of FIG. 2E eliminates the 180-degree turn paths from the internal connection Fi(k,2m+1) to the internal connection Uo(k,2m+1). Similarly the diagram 200E of FIG. 2E eliminates the 180-degree turn paths from the connection Fi(k,2m+2) to the connection Uo(k,2m+2). The diagram 200E of FIG. 2E eliminates the 180-degree turn paths from the internal connection Bi(k,2m+1) to the internal connection Ro(k,2m+1). Similarly the diagram 200E of FIG. 2E eliminates the 180-degree turn paths from the connection Bi(k,2m+2) to the connection Ro(k,2m+2). Hence diagram 200E of FIG. 2E comprises a forward switch, a backward switch, U-turn switch and reverse U-turn switch without 180-degree U-turn paths.

In contrast to diagram 200E of FIG. 2E, the diagram 200A of FIG. 2A, diagram 200B of FIG. 2B, and diagram 200C of FIG. 2C provide 180-degree U-turn paths. Two exemplary 180-degree U-turn paths in diagram 200A of FIG. 2A are shown (by two types of dotted lines) in the attached replacement diagram of FIG. 2A. One of the 180-degree turn path shown in the replacement diagram of FIG. 2A starts at the internal connection Fi(k,2m+1) through the Mux F(k,2m+1) to Fo(k,2m+1) through the Mux U(k,2m+1) to Uo(k,2m+1) through the Mux B(k,2m+1) to the internal connection Bo(k,2m+1). The second of the 180-degree turn path shown in the replacement diagram of FIG. 2A starts at the hop wire Fi(k,2m+2) through the Mux F(k,2m+2) to Fo(k,2m+2) through the Mux U(k,2m+2) to Uo(k,2m+2) through the Mux B(k, 2m+2) to the hop wire Bo(k,2m+2).

The stage “m” of ring “k” with “m” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 8 inputs and 4 outputs as shown in diagram 200F in FIG. 2F. FIG. 2F illustrates a stage (ring “k”, stage “m”) 200F consists of 8 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), Ui(k,2m+2), J, K, L, and M; and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of four 4:1 Muxes namely F(k,2m+1), F(k,2m+2), B(k,2m+1), and B(k,2m+2). The 4:1 Mux F(k,2m+1) has four inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+2), and J, and has one output Fo(k,2m+1). The 4:1 Mux F(k,2m+2) has four inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), and K, and has one output Fo(k,2m+2).

The 4:1 Mux B(k,2m+1) has four inputs namely Ui(k,2m+1), Ui(k,2m+2), Ri(k,2m+2), and L, and has one output Bo(k,2m+1). The 4:1 Mux B(k,2m+2) has four inputs namely Ui(k,2m+1), Ui(k,2m+2), Ri(k,2m+1) and M, and has one output Bo(k,2m+2). In different embodiments the inputs J, K, L, and M are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage “m” of ring “k” with “m” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 4 inputs and 4 outputs as shown in diagram 200G in FIG. 2G. FIG. 2G illustrates a stage (ring “k”, stage “m”) 200G consists of 4 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of four 3:1 Muxes namely F(k,2m+1), F(k,2m+2), B(k,2m+1), and B(k,2m+2). The 3:1 Mux F(k,2m+1) has three inputs namely Ri(k,2m+1), Ri(k,2m+2), and Ui(k,2m+2), and has one output Fo(k,2m+1). The 3:1 Mux F(k,2m+2) has three inputs namely Ri(k,2m+1), Ri(k,2m+2), and Ui(k,2m+1), and has one output Fo(k,2m+2).

The 3:1 Mux B(k,2m+1) has three inputs namely Ui(k,2m+1), Ui(k,2m+2), and Ri(k,2m+2), and has one output Bo(k,2m+1). The 3:1 Mux B(k,2m+2) has three inputs namely Ui(k,2m+1), Ui(k,2m+2), and Ri(k,2m+1), and has one output Bo(k,2m+2).

The stage “m” of ring “k” with “m” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 4 inputs and 4 outputs as shown in diagram 200H in FIG. 2H. FIG. 2H illustrates a stage (ring “k”, stage “m”) 200H consists of 4 inputs namely Ri(k,2m+1), Ri(k,2m+2), Bi(k,2m+1), Bi(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Ro(k,2m+1), and Ro(k,2m+2). The stage (ring “k”, stage “m”) also consists of four 2:1 Muxes namely R(k,2m+1), R(k,2m+2) (comprising in combination a Reverse U-turn switch), B(k,2m+1), and B(k,2m+2) (comprising in combination a backward switch). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+2), and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+1), and has one output Ro(k,2m+2).

The 2:1 Mux B(k,2m+1) has two inputs namely Bi(k,2m+1) and Bi(k,2m+2), and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Bi(k,2m+1) and Bi(k,2m+2), and has one output Bo(k,2m+2).

The stage “m” of ring “k” with “m” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 4 inputs and 4 outputs as shown in diagram 200I in FIG. 2I. FIG. 2I illustrates a stage (ring “k”, stage “m”) 200I consists of 4 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), Ui(k,2m+2); and 4 outputs Uo(k,2m+1), Uo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of two 3:1 Muxes namely F(k,2m+1), F(k,2m+2), and two 2:1 Muxes namely U(k,2m+1) and U(k,2m+2) (comprising in combination a U-turn switch). The 3:1 Mux F(k,2m+1) has three inputs namely Ri(k,2m+1), Ri(k,2m+2), and Ui(k,2m+2), and has one output Fo(k,2m+1). The 3:1 Mux F(k,2m+2) has three inputs namely Ri(k,2m+1), Ri(k,2m+2), and Ui(k,2m+1), and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+2), and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+1), and has one output Uo(k,2m+2).

The stage “m” of ring “k” with “m” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 4 inputs and 4 outputs as shown in diagram 200J in FIG. 2J. FIG. 2J illustrates a stage (ring “k”, stage “m”) 200J consists of 4 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Ro(k,2m+1), and Ro(k,2m+2). The stage (ring “k”, stage “m”) also consists of two 2:1 Muxes namely R(k,2m+1), R(k,2m+2) (comprising in combination a Reverse U-turn switch), and two 3:1 Muxes namely B(k,2m+1) and B(k,2m+2). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+2), and has one output Fo(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+1), and has one output Ro(k,2m+2).

The 3:1 Mux B(k,2m+1) has three inputs namely Ui(k,2m+1), Ui(k,2m+2) and Ri(k,2m+2), and has one output Bo(k,2m+1). The 3:1 Mux B(k,2m+2) has three inputs namely Ui(k,2m+1), Ui(k,2m+2) and Ri(k,2m+1), and has one output Bo(k,2m+2).

The diagram 200J of FIG. 2J eliminates the 180-degree turn paths from the internal connection Ri(k,2m+1) to the internal connection Bo(k,2m+1). Similarly the diagram 200J of FIG. 2J eliminates the 180-degree turn paths from the connection Ri(k,2m+2) to the connection Bo(k,2m+2). The diagram 200J of FIG. 2J eliminates the 180-degree turn paths from the internal connection Ui(k,2m+1) to the internal connection Ro(k,2m+1). Similarly the diagram 200J of FIG. 2J eliminates the 180-degree turn paths from the connection Ui(k,2m+2) to the connection Ro(k,2m+2). Hence diagram 200J of FIG. 2J comprises an integrated switch of a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree U-turn paths. Similarly the original diagram 200I of FIG. 2I also illustrate other embodiments of an integrated switch of a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree U-turn paths. Similarly the original diagrams 200F of FIG. 2F and 200G of FIG. 2G also illustrate other embodiments of an integrated switch of a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree U-turn paths.

The stage “n” of ring “2” with at least “n” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 14 inputs and 6 outputs as shown in diagram 200K in FIG. 2K. Stage number “n” may be any whole number. Similarly ring number “2” may be any whole number in general. FIG. 2K illustrates a stage (ring “2”, stage “n”) 200K consists of 14 inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n), Ui(2,2n+1), Ui(2,2n+2), J(2,n−1), K(2,n−1), L(2,n−1), M(2,n−1), J(2,n), K(2,n), L(2,n), and M(2,n); and 6 outputs Bo(2,2n−1), Bo(2,2n), Bo(2,2n+2), Fo(2,2n), Fo(2,2n+1) and Fo(2,2n+2). The stage (ring “2”, stage “n”) also consists of six 7:1 Muxes namely F(2,2n), F(2,2n+1), F(2,2n+2), B(2,2n−1), B(2,2n), and B(2,2n+2). The 7:1 Mux F(2,2n) has seven inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2), K(2,n−1), and L(2,n) and has one output Fo(2,2n). The 7:1 Mux B(2,2n−1) has seven inputs namely Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2), L(2,n−1), and L(2,n) and has one output Bo(2,2n−1). The 7:1 Mux B(2,2n) has seven inputs namely Ri(2,2n−1), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2), M(2,n−1), and L(2,n) and has one output Bo(2,2n).

The 7:1 Mux F(2,2n+1) has seven inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+2), J(2,n−1), and J(2,n) and has one output Fo(2,2n+1). The 7:1 Mux F(2,2n+2) has seven inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), J(2,n−1), and K(2,n) and has one output Fo(2,2n+2). The 7:1 Mux B(2,2n+2) has seven inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ui(2,2n+1), Ui(2,2n+2), J(2,n−1), and M(2,n) and has one output Bo(2,2n+2). In different embodiments the inputs J(2,n−1), K(2,n−1), L(2,n−1), M(2,n−1), J(2,n), K(2,n), L(2,n) and M(2,n) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage “n” of ring “2” with at least “n” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 6 inputs and 6 outputs as shown in diagram 200L in FIG. 2L. Stage number “n” may be any whole number. Similarly ring number “2” may be any whole number in general. FIG. 2L illustrates a stage (ring “2”, stage “n”) 200L consists of 6 inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n), Ui(2,2n+1) and Ui(2,2n+2); and 6 outputs Bo(2,2n−1), Bo(2,2n), Bo(2,2n+2), Fo(2,2n), Fo(2,2n+1) and Fo(2,2n+2). The stage (ring “2”, stage “n”) also consists of six 5:1 Muxes namely F(2,2n), F(2,2n+1), F(2,2n+2), B(2,2n−1), B(2,2n), and B(2,2n+2). The 5:1 Mux F(2,2n) has five inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n+1), and Ui(2,2n+2) and has one output Fo(2,2n). The 5:1 Mux B(2,2n−1) has five inputs namely Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), and Ui(2,2n+2) and has one output Bo(2,2n−1). The 5:1 Mux B(2,2n) has five inputs namely Ri(2,2n−1), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1) and Ui(2,2n+2) and has one output Bo(2,2n).

The 5:1 Mux F(2,2n+1) has five inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2) and Ui(2,2n+2) and has one output Fo(2,2n+1). The 5:1 Mux F(2,2n+2) has five inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2) and Ui(2,2n+1) and has one output Fo(2,2n+2). The 5:1 Mux B(2,2n+2) has five inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ui(2,2n+1) and Ui(2,2n+2) and has one output Bo(2,2n+2).

The stage “n” of ring “2” with at least “n” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 8 inputs and 6 outputs as shown in diagram 200M in FIG. 2M. Stage number “n” may be any whole number. Similarly ring number “2” may be any whole number in general. FIG. 2M illustrates a stage (ring “2”, stage “n”) 200M consists of 8 inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n), Ui(2,2n+1), Ui(2,2n+2), J(2,n−1) and L(2,n); and 6 outputs Bo(2,2n−1), Bo(2,2n), Bo(2,2n+2), Fo(2,2n), Fo(2,2n+1) and Fo(2,2n+2). The stage (ring “2”, stage “n”) also consists of six 6:1 Muxes namely F(2,2n), F(2,2n+1), F(2,2n+2), B(2,2n−1), B(2,2n), and B(2,2n+2). The 6:1 Mux F(2,2n) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2) and L(2,n) and has one output Fo(2,2n). The 6:1 Mux B(2,2n−1) has six inputs namely Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2) and L(2,n) and has one output Bo(2,2n−1). The 6:1 Mux B(2,2n) has six inputs namely Ri(2,2n−1), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2) and L(2,n) and has one output Bo(2,2n).

The 6:1 Mux F(2,2n+1) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+2), and J(2,n−1) and has one output Fo(2,2n+1). The 6:1 Mux F(2,2n+2) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1) and J(2,n−1) and has one output Fo(2,2n+2). The 6:1 Mux B(2,2n+2) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ui(2,2n+1), Ui(2,2n+2) and J(2,n−1) and has one output Bo(2,2n+2). In different embodiments the inputs J(2,n−1) and L(2,n) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage “n” of ring “2” with at least “n” stages of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), in another embodiment, may have 12 inputs and 6 outputs as shown in diagram 200N in FIG. 2N. Stage number “n” may be any whole number. Similarly ring number “2” may be any whole number in general. FIG. 2N illustrates a stage (ring “2”, stage “n”) 200N consists of 12 inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n), Ui(2,2n+1), Ui(2,2n+2), K(2,n−1), L(2,n−1), M(2,n−1), J(2,n), K(2,n), and M(2,n); and 6 outputs Bo(2,2n−1), Bo(2,2n), Bo(2,2n+2), Fo(2,2n), Fo(2,2n+1) and Fo(2,2n+2). The stage (ring “2”, stage “n”) also consists of six 6:1 Muxes namely F(2,2n), F(2,2n+1), F(2,2n+2), B(2,2n−1), B(2,2n), and B(2,2n+2). The 6:1 Mux F(2,2n) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2), and K(2,n−1) and has one output Fo(2,2n). The 6:1 Mux B(2,2n−1) has six inputs namely Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2), and L(2,n−1) and has one output Bo(2,2n−1). The 6:1 Mux B(2,2n) has six inputs namely Ri(2,2n−1), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1), Ui(2,2n+2), and M(2,n−1) and has one output Bo(2,2n).

The 6:1 Mux F(2,2n+1) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+2) and J(2,n) and has one output Fo(2,2n+1). The 6:1 Mux F(2,2n+2) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ri(2,2n+2), Ui(2,2n+1) and K(2,n) and has one output Fo(2,2n+2). The 6:1 Mux B(2,2n+2) has six inputs namely Ri(2,2n−1), Ri(2,2n), Ui(2,2n), Ui(2,2n+1), Ui(2,2n+2) and M(2,n) and has one output Bo(2,2n+2). In different embodiments the inputs K(2,n−1), L(2,n−1), M(2,n−1), J(2,n), K(2,n) and M(2,n) are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The number of stages in a ring of any block may not be equal to the number of stages in any other ring of the same of block or any ring of any other block of the multi-stage pyramid network V_(Comb)(N¹,N₂,d,s). For example the number of stages in ring 1 of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A or of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B or of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C is denoted by “m” and the number of stages in ring 2 of the partial multi-stage pyramid network is denoted by “n”, and so “m” may or may not be equal to “n”. Similarly the number of stages in ring 2 corresponding to block (3,3) of 2D-grid 800 may not be equal to the number of stages in ring 2 corresponding to block (6,9) of 2D-grid 800. Similarly in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C the number of stages in (slice 1, ring 2) corresponding to block (3,3) of 2D-grid 800 may not be equal to the number of stages in (slice 1, ring 2) corresponding to block (6,9) of 2D-grid 800.

Even though the number of inlet links to the computational block is four and the number of outlet links to the computational block is two in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A, the number of inlet links to the computational block is eight and the number of outlet links to the computational block is four in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B, and the number of inlet links to the computational block is sixteen and the number of outlet links to the computational block is four in the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C, in other embodiments the number of inlet links to the computational block may be any arbitrary number and the number of outlet links to the computational block may also be another arbitrary number. However the total number of rings of all the slices corresponding to the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) of a block is substantially equal to the number of inlet links to the computational block divided by d=2 if the inputs and outputs are connected either only from left-hand side or only from right-hand side, if the number of inlet links to the computational block is greater than or equal to the number of outlet links to the computational block. In such a case one or more of the outlet links to the computational block are connected to more than one inlet links of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to a block. Similarly the total number of rings of all the slices corresponding to the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) of a block is substantially equal to the number of inlet links to the computational block divided by 2*d=4 if the inputs and outputs are connected from both left-hand side and from right-hand side, if the number of inlet links to the computational block is greater than or equal to the number of outlet links to the computational block. In both these two embodiments the number stages in each ring can still be optimized or reduced in number. Furthermore in both these embodiments d itself may not be constant and vary from stage to stag and also with in a stage.

Otherwise the total number of rings of all the slices corresponding to the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) of a block is substantially equal to the number of outlet links to the computational block divided by d=2 if the inputs and outputs are connected either only from left-hand side or only from right-hand side, if the number of outlet links to the computational block is greater than the number of inlet links to the computational block. In such a case one or more of the outlet links of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to a block are connected to more than one inlet link of the computational block. Similarly the total number of rings of all the slices corresponding to the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) of a block, when d is a constant, is substantially equal to the number of outlet links to the computational block divided by 2*d=4 if the inputs and outputs are connected from both left-hand side and from right-hand side, if the number of outlet links to the computational block is greater than or equal to the number of inlet links to the computational block.

In another embodiment, the number of inlet links to the computational block corresponding to a block of 2D-grid of blocks may or may not be equal to the number of inlet links to the computational block corresponding to another block. Similarly the number of outlet links to the computational block corresponding to a block of 2D-grid of blocks may or may not be equal to the number of outlet links to the computational block corresponding to another block. Hence the total number of rings of the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to a block of 2D-grid of blocks may or may not be equal to the partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) corresponding to another block. For example the total number of rings corresponding to block (4,5) of 2D-grid 800 may be two and the total number of rings in block (5,4) of 2D-grid 800 may be three.

A multi-stage pyramid network can be represented with the notation V_(Comb)(N₁,N₂,d,s), where N₁ represents the total number of inlet links of the complete multi-stage pyramid network and N₂ represents the total number of outlet links of the complete multi-stage pyramid network, d represents the number of inlet links of any ring in any block of the complete multi-stage pyramid network either from only left-hand side or only right-hand side, or equivalently the number of outlet links of any ring in any block of the complete multi-stage pyramid network either from only left-hand side or only right-hand side, and when the inputs and outputs are connected from left-hand side, (However size of each stage may be different and size of each mux in a stage also may be different from other muxes in the same switch, furthermore each size may be depopulated.), s is the ratio of number of outgoing links from each stage 0 of any ring in any block to the number of inlet links of any ring in any block of the complete multi-stage pyramid network (for example the complete multi-stage pyramid network corresponding to V_(Comb)(N₁,N₂,d,s) 100A in FIG. 1A, N₁=200, N₂=400, d=2, s=1). Also a multi-stage pyramid network where N₁=N₂=N is represented as V_(Comb)(N,d,s).

The diagram 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, and 300E of FIG. 3E are different embodiments of all the connections between two arbitrary successive stages in two different rings of the same block or two different rings of different blocks of 2D-grid 800. Referring to diagram 300A in FIG. 3A illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 4 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), and Ui(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of eight 2:1 Muxes namely R(x,2p+1), R(x,2p+2), F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux R(x,2p+1) has two inputs namely Ri(x,2p+1) and Bo(x,2p+1) and has one output Ro(x,2p+1). The 2:1 Mux R(x,2p+2) has two inputs namely Ri(x,2p+2) and Bo(x,2p+2) and has one output Ro(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Ro(x,2p+1) and Ro(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Ro(x,2p+1) and Ro(x,2p+2) and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and Fo(x,2p+1) and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 4 inputs namely Ri(x,2p+3), Ri(x,2p+4), Ui(x,2p+3), and Ui(x,2p+4); and 4 outputs Bo(x,2p+3), Bo(x,2p+4), Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of eight 2:1 Muxes namely R(x,2p+3), R(x,2p+4), F(x,2p+3), F(x,2p+4), U(x,2p+3), U(x,2p+4), B(x,2p+3), and B(x,2p+4). The 2:1 Mux R(x,2p+3) has two inputs namely Ri(x,2p+3) and Bo(x,2p+3) and has one output Ro(x,2p+3). The 2:1 Mux R(x,2p+4) has two inputs namely Ri(x,2p+4) and Bo(x,2p+4) and has one output Ro(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely Ro(x,2p+3) and Ro(x,2p+4) and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely Ro(x,2p+3) and Ro(x,2p+4) and has one output Fo(x,2p+4).

The 2:1 Mux U(x,2p+3) has two inputs namely Ui(x,2p+3) and Fo(x,2p+3) and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Ui(x,2p+4) and Fo(x,2p+4) and has one output Uo(x,2p+4). The 2:1 Mux B(x,2p+3) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Ri(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Bo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 4 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), and Ui(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of eight 2:1 Muxes namely R(y,2q+1), R(y,2q+2), F(y,2q+1), F(y,2q+2), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux R(y,2q+1) has two inputs namely Ri(y,2q+1) and Bo(y,2q+1) and has one output Ro(y,2q+1). The 2:1 Mux R(y,2q+2) has two inputs namely Ri(y,2q+2) and Bo(y,2q+2) and has one output Ro(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Ro(y,2q+1) and Ro(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Ro(y,2q+1) and Ro(y,2q+2) and has one output Fo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and Fo(y,2q+1) and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 4 inputs namely Ri(y,2q+3), Ri(y,2q+4), Ui(y,2q+3), and Ui(y,2q+4); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of eight 2:1 Muxes namely R(y,2q+3), R(y,2q+4), F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux R(y,2q+3) has two inputs namely Ri(y,2q+3) and Bo(y,2q+3) and has one output Ro(y,2q+3). The 2:1 Mux R(y,2q+4) has two inputs namely Ri(y,2q+4) and Bo(y,2q+4) and has one output Ro(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely Ro(y,2q+3) and Ro(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely Ro(y,2q+3) and Ro(y,2q+4) and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and Fo(y,2q+3) and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Ri(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Ri(y,2q+4) of the stage (ring “y”, stage “q+1”). The output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to the input Ui(y,2q+2) of the stage (ring “y”, stage “q”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to the input Ri(x,2p+4) of the stage (ring “x”, stage “p+1”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

Ring “x” and ring “y” may or may not belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). If ring “x” and ring “y” belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are hereinafter called “internal hop wires”. For example if “x=2” and “y=3” and both the ring 2 and ring 3 belong to the same block (9,9) of 2D-grid 800, then the wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are “internal hop wires”.

If ring “x” and ring “y” belong to the different blocks of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are hereinafter called “external hop wires”. The external hop wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) may be horizontal wires or vertical wires. The length of the external hop wires is Manhattan distance between the corresponding blocks, hereinafter “hop length”. For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (1,6) of 2D-grid 800 then the external hop wires are hereinafter called “horizontal external hop wires”. And the hop length of the horizontal hop wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) is given by 6−1=5. Similarly if ring “x” and ring “y” belong to two blocks in the same horizontal row of 2D-grid 800, then the wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are horizontal external hop wires.

For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (9,1) of 2D-grid 800 then the external hop wires are hereinafter called “vertical external hop wires”. And the hop length of the vertical hop wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) is given by 9−1=8. Similarly if ring “x” and ring “y” belong to two blocks in the same vertical column of 2D-grid 800, then the wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are vertical external hop wires. External hop wires are substantially horizontal or vertical according to the current invention.

Referring to diagram 300B in FIG. 3B illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 8 inputs namely Fi(x,2p+1), Fi(x,2p+2), Bi(x,2p+1), Bi(x,2p+2), J1, K1, L1, and M1; and 4 outputs Uo(x,2p+1), Uo(x,2p+2), Ro(x,2p+1), and Ro(x,2p+2). The stage (ring “x”, stage “p’) also consists of eight 2:1 Muxes namely F(x,2p+1), F(x,2p+2), R(x,2p+1), R(x,2p+2), B(x,2p+1), B(x,2p+2), U(x,2p+1), and U(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Fi(x,2p+1) and J1, and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Fi(x,2p+2) and K1, and has one output Fo(x,2p+2). The 2:1 Mux R(x,2p+1) has two inputs namely Fo(x,2p+1) and Bo(x,2p+2), and has one output Ro(x,2p+1). The 2:1 Mux R(x,2p+2) has two inputs namely Fo(x,2p+2) and Bo(x,2p+1), and has one output Ro(x,2p+2).

The 2:1 Mux B(x,2p+1) has two inputs namely Bi(x,2p+1) and L1, and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Bi(x,2p+2) and M1, and has one output Bo(x,2p+2). The 2:1 Mux U(x,2p+1) has two inputs namely Bo(x,2p+1) and Fo(x,2p+2), and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Bo(x,2p+2) and Fo(x,2p+1), and has one output Uo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 8 inputs namely Fi(x,2p+3), Fi(x,2p+4), Bi(x,2p+3), Bi(x,2p+4), J2, K2, L2, and M2; and 4 outputs Uo(x,2p+3), Uo(x,2p+4), Ro(x,2p+3), and Ro(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of eight 2:1 Muxes namely F(x,2p+3), F(x,2p+4), R(x,2p+3), R(x,2p+4), B(x,2p+3), B(x,2p+4), U(x,2p+3), and U(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely Fi(x,2p+3) and J2, and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely Fi(x,2p+4) and K2, and has one output Fo(x,2p+4). The 2:1 Mux R(x,2p+3) has two inputs namely Fo(x,2p+3) and Bo(x,2p+4), and has one output Ro(x,2p+3). The 2:1 Mux R(x,2p+4) has two inputs namely Fo(x,2p+4) and Bo(x,2p+3), and has one output Ro(x,2p+4).

The 2:1 Mux B(x,2p+3) has two inputs namely Bi(x,2p+3) and L2, and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Bi(x,2p+4) and M2, and has one output Bo(x,2p+4). The 2:1 Mux U(x,2p+3) has two inputs namely Bo(x,2p+3) and Fo(x,2p+4), and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Bo(x,2p+4) and Fo(x,2p+3), and has one output Uo(x,2p+4).

The output Ro(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Fi(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Uo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Bi(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 8 inputs namely Fi(y,2q+1), Fi(y,2q+2), Bi(y,2q+1), Bi(y,2q+2), J3, K3, L3, and M3; and 4 outputs Uo(y,2q+1), Uo(y,2q+2), Ro(y,2q+1), and Ro(y,2q+2). The stage (ring “y”, stage “q’) also consists of eight 2:1 Muxes namely F(y,2q+1), F(y,2q+2), R(y,2q+1), R(y,2q+2), B(y,2q+1), B(y,2q+2), U(y,2q+1), and U(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Fi(y,2q+1) and J3, and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Fi(y,2q+2) and K3, and has one output Fo(y,2q+2). The 2:1 Mux R(y,2q+1) has two inputs namely Fo(y,2q+1) and Bo(y,2q+2), and has one output Ro(y,2q+1). The 2:1 Mux R(y,2q+2) has two inputs namely Fo(y,2q+2) and Bo(y,2q+1) and has one output Ro(y,2q+2).

The 2:1 Mux B(y,2q+1) has two inputs namely Bi(y,2q+1) and L3, and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Bi(y,2q+2) and M3, and has one output Bo(y,2q+2). The 2:1 Mux U(y,2q+1) has two inputs namely Bo(y,2q+1) and Fo(y,2q+2), and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Bo(y,2q+2) and Fo(y,2q+1), and has one output Uo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 8 inputs namely Fi(y,2q+3), Fi(y,2q+4), Bi(y,2q+3), Bi(y,2q+4), J4, K4, L4, and M4; and 4 outputs Uo(y,2q+3), Uo(y,2q+4), Ro(y,2q+3), and Ro(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of eight 2:1 Muxes namely F(y,2q+3), F(y,2q+4), R(y,2q+3), R(y,2q+4), B(y,2q+3), B(y,2q+4), U(y,2q+3), and U(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely Fi(y,2q+3) and J4, and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely Fi(y,2q+4) and K4, and has one output Fo(y,2q+4). The 2:1 Mux R(y,2q+3) has two inputs namely Fo(y,2q+3) and Bo(y,2q+4), and has one output Ro(y,2q+3). The 2:1 Mux R(y,2q+4) has two inputs namely Fo(y,2q+4) and Bo(y,2q+3), and has one output Ro(y,2q+4).

The 2:1 Mux B(y,2q+3) has two inputs namely Bi(y,2q+3) and L4, and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Bi(y,2q+4) and M4, and has one output Bo(y,2q+4). The 2:1 Mux U(y,2q+3) has two inputs namely Bo(y,2q+3) and Fo(y,2q+4), and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Bo(y,2q+4) and Fo(y,2q+3), and has one output Uo(y,2q+4).

The output Ro(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Fi(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Uo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Bi(y,2q+1) of the stage (ring “y”, stage “q”).

The output Uo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Bi(y,2q+2) of the stage (ring “y”, stage “q”). The output Ro(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(1,2) to the input Fi(x,2p+2) of the stage (ring “x”, stage “p”).

The output Uo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(2,1) to the input Bi(y,2q+4) of the stage (ring “y”, stage “q+1”). The output Ro(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to the input Fi(x,2p+4) of the stage (ring “x”, stage “p+1”).

In various embodiments, the inputs J1, K1, L1, and M1 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Similarly the inputs J2, K2, L2, and M2 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Similarly the inputs J3, K3, L3, and M3 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Finally the inputs J4, K4, L4, and M4 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

Referring to diagram 300C in FIG. 3C, illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 4 inputs namely Fi(x,2p+1), Fi(x,2p+2), Ui(x,2p+1), and Ui(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of six 2:1 Muxes namely F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and Fo(x,2p+1) and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 4 inputs namely Fi(x,2p+3), Fi(x,2p+4), Ui(x,2p+3), and Ui(x,2p+4); and 4 outputs Bo(x,2p+3), Bo(x,2p+4), Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of six 2:1 Muxes namely F(x,2p+3), F(x,2p+4), U(x,2p+3), U(x,2p+4), B(x,2p+3), and B(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely Fi(x,2p+3) and Fi(x,2p+4) and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely Fi(x,2p+3) and Fi(x,2p+4) and has one output Fo(x,2p+4).

The 2:1 Mux U(x,2p+3) has two inputs namely Ui(x,2p+3) and Fo(x,2p+3) and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Ui(x,2p+4) and Fo(x,2p+4) and has one output Uo(x,2p+4). The 2:1 Mux B(x,2p+3) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Fi(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Bo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 4 inputs namely Fi(y,2q+1), Fi(y,2q+2), Ui(y,2q+1), and Ui(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of six 2:1 Muxes namely F(y,2q+1), F(y,2q+2), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and Fo(y,2q+1) and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 4 inputs namely Fi(y,2q+3), Fi(y,2q+4), Ui(y,2q+3), and Ui(y,2q+4); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of six 2:1 Muxes namely F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely Fi(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely Fi(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and Fo(y,2q+3) and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Fi(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Fi(y,2q+4) of the stage (ring “y”, stage “q+1”). The output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to the input Ui(y,2q+2) of the stage (ring “y”, stage “q”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to the input Fi(x,2p+4) of the stage (ring “x”, stage “p+1”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

Referring to diagram 300D in FIG. 3D, illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 4 inputs namely Fi(x,2p+1), Fi(x,2p+2), Ui(x,2p+1), and Ui(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of six 2:1 Muxes namely F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and Fo(x,2p+1) and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 2 inputs namely Fi(x,2p+3), Fi(x,2p+4); and 2 outputs Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of two 2:1 Muxes namely F(x,2p+3) and F(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely Fi(x,2p+3) and Fi(x,2p+4) and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely Fi(x,2p+3) and Fi(x,2p+4) and has one output Fo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Fi(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Fo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 4 inputs namely Fi(y,2q+1), Fi(y,2q+2), Ui(y,2q+1), and Ui(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of six 2:1 Muxes namely F(y,2q+1), F(y,2q+2), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and Fo(y,2q+1) and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 4 inputs namely Fi(y,2q+3), Fi(y,2q+4), Ui(y,2q+3), and Ui(y,2q+4); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of six 2:1 Muxes namely F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely Fi(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely Fi(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and Fo(y,2q+3) and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Fi(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Fi(y,2q+4) of the stage (ring “y”, stage “q+1”). The output Fo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to the input Ui(y,2q+2) of the stage (ring “y”, stage “q”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to the input Fi(x,2p+4) of the stage (ring “x”, stage “p+1”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

Referring to diagram 300E in FIG. 3E, illustrates all the connections between root stage of a ring namely the stage (ring “x”, stage “p”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 4 inputs namely Fi(x,2p+1), Fi(x,2p+2), Ui(x,2p+1), and Ui(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of six 2:1 Muxes namely F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and Fo(x,2p+1) and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+2).

The stage (ring “y”, stage “q”) consists of 4 inputs namely Fi(y,2q+1), Fi(y,2q+2), Ui(y,2q+1), and Ui(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of six 2:1 Muxes namely F(y,2q+1), F(y,2q+2), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and Fo(y,2q+1) and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 4 inputs namely Fi(y,2q+3), Fi(y,2q+4), Ui(y,2q+3), and Ui(y,2q+4); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of six 2:1 Muxes namely F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely Fi(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely Fi(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and Fo(y,2q+3) and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Fi(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,2) to the input Ui(y,2q+2) of the stage (ring “y”, stage “q”). The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Fi(y,2q+4) of the stage (ring “y”, stage “q+1”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

Just like in diagram 300A of FIG. 3A, in diagram 300B of FIG. 3B, in diagram 300C of FIG. 3C, diagram 300D of FIG. 3D, and in diagram 300E of FIG. 3E, the wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are either internal hop wires or horizontal external hop wires or vertical external hop wires (hereinafter alternatively referred to as “cross links” or “cross middle links”).

The diagram 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C and 400D of FIG. 4D are different embodiments of all the connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks of 2D-grid 800. Referring to diagram 400A in FIG. 4A illustrates all the connections between an arbitrary stage of a ring namely the stages (ring “x”, stage “p”), and another arbitrary stage of any other ring namely the stages (ring “y”, stage “q”) of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where x, y, p and q all four are any whole numbers. In one embodiment p is equal to q and in another embodiment p is not equal to q.

The stage (ring “x”, stage “p”) consists of 8 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2), J1, K1, L1, and M1; and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of eight 2:1 Muxes namely R(x,2p+1), R(x,2p+2), F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux R(x,2p+1) has two inputs namely Ri(x,2p+1) and J1 and has one output Ro(x,2p+1). The 2:1 Mux R(x,2p+2) has two inputs namely Ri(x,2p+2) and K1 and has one output Ro(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Ro(x,2p+1) and Uo(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Ro(x,2p+2) and Uo(x,2p+1) and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and L1 and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and M1 and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Ro(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+2) and Ro(x,2p+1) and has one output Bo(x,2p+2).

The stage (ring “y”, stage “q”) consists of 8 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), Ui(y,2q+2), J3, K3, L3, and M3; and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of eight 2:1 Muxes namely R(y,2q+1), R(y,2q+2), F(y,2q+1), F(y,2q+2), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux R(y,2q+1) has two inputs namely Ri(y,2q+1) and J3 and has one output Ro(y,2q+1). The 2:1 Mux R(y,2q+2) has two inputs namely Ri(y,2q+2) and K3 and has one output Ro(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Ro(y,2q+1) and Uo(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Ro(y,2q+2) and Uo(y,2q+1) and has one output Fo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and L3, and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and M3, and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Ro(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+2) and Ro(y,2q+1) and has one output Bo(y,2q+2).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Ri(y,2q+2) of the stage (ring “y”, stage “q”). The output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(1,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

Ring “x” and ring “y” may or may not belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). If ring “x” and ring “y” belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “internal hop wires”. For example if “x=2” and “y=3” and both the ring 2 and ring 3 belong to the same block (9,9) of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are “internal hop wires”.

If ring “x” and ring “y” belong to the different blocks of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “external hop wires”. The external hop wires Hop(1,1) and Hop(1,2) may be horizontal wires or vertical wires. The length of the external hop wires is Manhattan distance between the corresponding blocks, hereinafter “hop length”. For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (1,6) of 2D-grid 800 then the external hop wires are hereinafter called “horizontal external hop wires”. And the hop length of the horizontal hop wires Hop(1,1) and Hop(1,2) is given by 6−1=5. Similarly if ring “x” and ring “y” belong to two blocks in the same horizontal row of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are horizontal external hop wires.

For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (9,1) of 2D-grid 800 then the external hop wires are hereinafter called “vertical external hop wires”. And the hop length of the vertical hop wires Hop(1,1) and Hop(1,2) is given by 9−1=8. Similarly if ring “x” and ring “y” belong to two blocks in the same vertical column of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are vertical external hop wires. External hop wires are substantially horizontal or vertical according to the current invention.

Referring to diagram 400B in FIG. 4B illustrates all the connections between an arbitrary stage of a ring namely the stages (ring “x”, stage “p”), and another arbitrary stage of any other ring namely the stages (ring “y”, stage “q”) of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where x, y, p and q all four are any whole numbers. In one embodiment p is equal to q and in another embodiment p is not equal to q.

The stage (ring “x”, stage “p”) consists of 8 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2), J1, K1, L1, and M1; and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of four 4:1 Muxes namely F(x,2p+1), F(x,2p+2), B(x,2p+1), and B(x,2p+2). The 4:1 Mux F(x,2p+1) has four inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+2), and J1 and has one output Fo(x,2p+1). The 4:1 Mux F(x,2p+2) has four inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), and K1 and has one output Fo(x,2p+2).

The 4:1 Mux B(x,2p+1) has four inputs namely Ui(x,2p+1), Ui(x,2p+2), Ri(x,2p+2), and L1 and has one output Bo(x,2p+1). The 4:1 Mux B(x,2p+2) has four inputs namely Ui(x,2p+1), Ui(x,2p+2), Ri(x,2p+1), and M1 and has one output Bo(x,2p+2).

The stage (ring “y”, stage “q”) consists of 8 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), Ui(y,2q+2), J3, K3, L3, and M3; and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of four 4:1 Muxes namely F(y,2q+1), F(y,2q+2), B(y,2q+1), and B(y,2q+2). The 4:1 Mux F(y,2q+1) has four inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+2), and J3 and has one output Fo(y,2q+1). The 4:1 Mux F(y,2q+2) has four inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), and K3 and has one output Fo(y,2q+2).

The 4:1 Mux B(y,2q+1) has four inputs namely Ui(y,2q+1), Ui(y,2q+2), Ri(y,2q+2), and L3, and has one output Bo(y,2q+1). The 4:1 Mux B(y,2q+2) has four inputs namely Ui(y,2q+1), Ui(y,2q+2), Ri(y,2q+1), and M3, and has one output Bo(y,2q+2).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Ri(y,2q+2) of the stage (ring “y”, stage “q”). The output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(1,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

Ring “x” and ring “y” may or may not belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). If ring “x” and ring “y” belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “internal hop wires”. For example if “x=2” and “y=3” and both the ring 2 and ring 3 belong to the same block (9,9) of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are “internal hop wires”.

If ring “x” and ring “y” belong to the different blocks of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “external hop wires”. The external hop wires Hop(1,1) and Hop(1,2) may be horizontal wires or vertical wires. The length of the external hop wires is Manhattan distance between the corresponding blocks, hereinafter “hop length”. For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (1,6) of 2D-grid 800 then the external hop wires are hereinafter called “horizontal external hop wires”. And the hop length of the horizontal hop wires Hop(1,1) and Hop(1,2) is given by 6−1=5. Similarly if ring “x” and ring “y” belong to two blocks in the same horizontal row of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are horizontal external hop wires.

For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (9,1) of 2D-grid 800 then the external hop wires are hereinafter called “vertical external hop wires”. And the hop length of the vertical hop wires Hop(1,1) and Hop(1,2) is given by 9−1=8. Similarly if ring “x” and ring “y” belong to two blocks in the same vertical column of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are vertical external hop wires. External hop wires are substantially horizontal or vertical according to the current invention.

Referring to diagram 400C in FIG. 4C illustrates all the connections between an arbitrary stage of a ring namely the stages (ring “x”, stage “p”), and another arbitrary stage of any other ring namely the stages (ring “y”, stage “q”) of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where x, y, p and q all four are any whole numbers. In one embodiment p is equal to q and in another embodiment p is not equal to q.

The stage (ring “x”, stage “p”) consists of 4 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of four 3:1 Muxes namely F(x,2p+1), F(x,2p+2), B(x,2p+1), and B(x,2p+2). The 3:1 Mux F(x,2p+1) has three inputs namely Ri(x,2p+1), Ri(x,2p+2), and Ui(x,2p+2), and has one output Fo(x,2p+1). The 3:1 Mux F(x,2p+2) has three inputs namely Ri(x,2p+1), Ri(x,2p+2), and Ui(x,2p+1), and has one output Fo(x,2p+2).

The 3:1 Mux B(x,2p+1) has three inputs namely Ui(x,2p+1), Ui(x,2p+2), and Ri(x,2p+2), and has one output Bo(x,2p+1). The 3:1 Mux B(x,2p+2) has three inputs namely Ui(x,2p+1), Ui(x,2p+2), and Ri(x,2p+1), and has one output Bo(x,2p+2).

The stage (ring “y”, stage “q”) consists of 4 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), Ui(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of four 3:1 Muxes namely F(y,2q+1), F(y,2q+2), B(y,2q+1), and B(y,2q+2). The 3:1 Mux F(y,2q+1) has three inputs namely Ri(y,2q+1), Ri(y,2q+2), and Ui(y,2q+2), and has one output Fo(y,2q+1). The 3:1 Mux F(y,2q+2) has three inputs namely Ri(y,2q+1), Ri(y,2q+2), and Ui(y,2q+1), and has one output Fo(y,2q+2).

The 3:1 Mux B(y,2q+1) has three inputs namely Ui(y,2q+1), Ui(y,2q+2), and Ri(y,2q+2), and has one output Bo(y,2q+1). The 3:1 Mux B(y,2q+2) has three inputs namely Ui(y,2q+1), Ui(y,2q+2), and Ri(y,2q+1), and has one output Bo(y,2q+2).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Ri(y,2q+2) of the stage (ring “y”, stage “q”). The output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(1,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

Ring “x” and ring “y” may or may not belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). If ring “x” and ring “y” belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “internal hop wires”. For example if “x=2” and “y=3” and both the ring 2 and ring 3 belong to the same block (9,9) of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are “internal hop wires”.

If ring “x” and ring “y” belong to the different blocks of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “external hop wires”. The external hop wires Hop(1,1) and Hop(1,2) may be horizontal wires or vertical wires. The length of the external hop wires is Manhattan distance between the corresponding blocks, hereinafter “hop length”. For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (1,6) of 2D-grid 800 then the external hop wires are hereinafter called “horizontal external hop wires”. And the hop length of the horizontal hop wires Hop(1,1) and Hop(1,2) is given by 6−1=5. Similarly if ring “x” and ring “y” belong to two blocks in the same horizontal row of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are horizontal external hop wires.

For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (9,1) of 2D-grid 800 then the external hop wires are hereinafter called “vertical external hop wires”. And the hop length of the vertical hop wires Hop(1,1) and Hop(1,2) is given by 9−1=8. Similarly if ring “x” and ring “y” belong to two blocks in the same vertical column of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are vertical external hop wires. External hop wires are substantially horizontal or vertical according to the current invention.

Referring to diagram 400D in FIG. 4D illustrates all the connections between an arbitrary stage of a ring namely the stages (ring “x”, stage “p”), and another arbitrary stage of any other ring namely the stages (ring “y”, stage “q”) of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) where x, y, p and q all four are any whole numbers. In one embodiment p is equal to q and in another embodiment p is not equal to q.

The stage (ring “x”, stage “p”) consists of 4 inputs namely Fi(x,2p+1), Fi(x,2p+2), Bi(x,2p+1), Bi(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of four 2:1 Muxes namely F(x,2p+1), F(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2), and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2), and has one output Fo(x,2p+2).

The 2:1 Mux B(x,2p+1) has two inputs namely Bi(x,2p+1) and Fo(x,2p+2), and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Bi(x,2p+2) and Fo(x,2p+1), and has one output Bo(x,2p+2).

The stage (ring “y”, stage “q”) consists of 4 inputs namely Fi(y,2q+1), Fi(y,2q+2), Bi(y,2q+1), Bi(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of four 2:1 Muxes namely F(y,2q+1), F(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2), and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2), and has one output Fo(y,2q+2).

The 2:1 Mux B(y,2q+1) has two inputs namely Bi(y,2q+1) and Fo(y,2q+2), and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+1), and has one output Bo(y,2q+2).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Fi(y,2q+2) of the stage (ring “y”, stage “q”). The output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(1,2) to the input Bi(x,2p+2) of the stage (ring “x”, stage “p”).

Ring “x” and ring “y” may or may not belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). If ring “x” and ring “y” belong to the same block of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “internal hop wires”. For example if “x=2” and “y=3” and both the ring 2 and ring 3 belong to the same block (9,9) of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are “internal hop wires”.

If ring “x” and ring “y” belong to the different blocks of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s), then the wires Hop(1,1) and Hop(1,2) are hereinafter called “external hop wires”. The external hop wires Hop(1,1) and Hop(1,2) may be horizontal wires or vertical wires. The length of the external hop wires is Manhattan distance between the corresponding blocks, hereinafter “hop length”. For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (1,6) of 2D-grid 800 then the external hop wires are hereinafter called “horizontal external hop wires”. And the hop length of the horizontal hop wires Hop(1,1) and Hop(1,2) is given by 6−1=5. Similarly if ring “x” and ring “y” belong to two blocks in the same horizontal row of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are horizontal external hop wires.

For example if ring “x” belongs to block (1,1) and ring “y” belongs to block (9,1) of 2D-grid 800 then the external hop wires are hereinafter called “vertical external hop wires”. And the hop length of the vertical hop wires Hop(1,1) and Hop(1,2) is given by 9−1=8. Similarly if ring “x” and ring “y” belong to two blocks in the same vertical column of 2D-grid 800, then the wires Hop(1,1) and Hop(1,2) are vertical external hop wires. External hop wires are substantially horizontal or vertical according to the current invention.

The diagram 500A of FIG. 5A is an embodiments of all the connections with multi-drop hop wires, between two arbitrary successive stages in two different rings of different blocks of 2D-grid 800. Referring to diagram 500A in FIG. 5A illustrates all the connections with multi-drop hop wires, between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). The multi-drop hop wires are also connected to two other stages (ring “a”, stage “s”) and (ring “b”, stage “t”) belonging to a third block.

The stage (ring “x”, stage “p”) consists of 8 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2), J1, K1, L1, and M1; and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of eight 2:1 Muxes namely R(x,2p+1), R(x,2p+2), F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux R(x,2p+1) has two inputs namely Ri(x,2p+1) and J1, and has one output Ro(x,2p+1). The 2:1 Mux R(x,2p+2) has two inputs namely Ri(x,2p+2) and K1, and has one output Ro(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Ro(x,2p+1) and Uo(x,2p+2), and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Ro(x,2p+2) and Uo(x,2p+1), and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and L1, and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and M1, and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Ro(x,2p+2), and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+2) and Ro(x,2p+1), and has one output Bo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 8 inputs namely Ri(x,2p+3), Ri(x,2p+4), Ui(x,2p+3), Ui(x,2p+4), J2, K2, L2, and M2; and 4 outputs Bo(x,2p+3), Bo(x,2p+4), Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of eight 2:1 Muxes namely R(x,2p+3), R(x,2p+4), F(x,2p+3), F(x,2p+4), U(x,2p+3), U(x,2p+4), B(x,2p+3), and B(x,2p+4). The 2:1 Mux R(x,2p+3) has two inputs namely Ri(x,2p+3) and J2, and has one output Ro(x,2p+3). The 2:1 Mux R(x,2p+4) has two inputs namely Ri(x,2p+4) and K2, and has one output Ro(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely Ro(x,2p+3) and Uo(x,2p+4), and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely Ro(x,2p+4) and Uo(x,2p+3), and has one output Fo(x,2p+4).

The 2:1 Mux U(x,2p+3) has two inputs namely Ui(x,2p+3) and L2, and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Ui(x,2p+4) and M2, and has one output Uo(x,2p+4). The 2:1 Mux B(x,2p+3) has two inputs namely Uo(x,2p+3) and Ro(x,2p+4), and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Uo(x,2p+4) and Ro(x,2p+3), and has one output Bo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Ri(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Bo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 8 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), Ui(y,2q+2), J3, K3, L3, and M3; and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of eight 2:1 Muxes namely R(y,2q+1), R(y,2q+2), F(y,2q+1), F(y,2q+2), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux R(y,2q+1) has two inputs namely Ri(y,2q+1) and J3, and has one output Ro(y,2q+1). The 2:1 Mux R(y,2q+2) has two inputs namely Ri(y,2q+2) and K3, and has one output Ro(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Ro(y,2q+1) and Uo(y,2q+2), and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Ro(y,2q+2) and Uo(y,2q+1) and has one output Fo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and L3, and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and M3, and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Ro(y,2q+2), and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+2) and Ro(y,2q+1), and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 8 inputs namely Ri(y,2q+3), Ri(y,2q+4), Ui(y,2q+3), Ui(y,2q+4), J4, K4, L4, and M4; and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of eight 2:1 Muxes namely R(y,2q+3), R(y,2q+4), F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux R(y,2q+3) has two inputs namely Ri(y,2q+3) and J4, and has one output Ro(y,2q+3). The 2:1 Mux R(y,2q+4) has two inputs namely Ri(y,2q+4) and K4, and has one output Ro(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely Ro(y,2q+3) and Uo(y,2q+4), and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely Ro(y,2q+4) and Uo(y,2q+3), and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and L4, and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and M4, and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Ro(y,2q+4), and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+4) and Ro(y,2q+3), and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Ri(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Ri(y,2q+4) of the stage (ring “y”, stage “q+1”). The output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to the input Ui(y,2q+2) of the stage (ring “y”, stage “q”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to the input Ri(x,2p+4) of the stage (ring “x”, stage “p+1”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

In various embodiments, the inputs J1, K1, L1, and M1 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Similarly the inputs J2, K2, L2, and M2 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Similarly the inputs J3, K3, L3, and M3 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Finally the inputs J4, K4, L4, and M4 are connected from any of the outputs of any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The stage (ring “a”, stage “s”) consists of 8 inputs namely Ri(a,2s+1), Ri(a,2s+2), Ui(a,2s+1), Ui(a,2s+2), J5, K5, L5, and M5; and 4 outputs Bo(a,2s+1), Bo(a,2s+2), Fo(a,2s+1), and Fo(a,2s+2). The stage (ring “a”, stage “s’) also consists of eight 2:1 Muxes namely R(a,2s+1), R(a,2s+2), F(a,2s+1), F(a,2s+2), U(a,2s+1), U(a,2s+2), B(a,2s+1), and B(a,2s+2). The 2:1 Mux R(a,2s+1) has two inputs namely Ri(a,2s+1) and J5, and has one output Ro(a,2s+1). The 2:1 Mux R(a,2s+2) has two inputs namely Ri(a,2s+2) and K5, and has one output Ro(a,2s+2). The 2:1 Mux F(a,2s+1) has two inputs namely Ro(a,2s+1) and Uo(a,2s+2), and has one output Fo(a,2s+1). The 2:1 Mux F(a,2s+2) has two inputs namely Ro(a,2s+2) and Uo(a,2s+1), and has one output Fo(a,2s+2).

The 2:1 Mux U(a,2s+1) has two inputs namely Ui(a,2s+1) and L5, and has one output Uo(a,2s+1). The 2:1 Mux U(a,2s+2) has two inputs namely Ui(a,2s+2) and M5, and has one output Uo(a,2s+2). The 2:1 Mux B(a,2s+1) has two inputs namely Uo(a,2s+1) and Ro(a,2s+2), and has one output Bo(a,2s+1). The 2:1 Mux B(a,2s+2) has two inputs namely Uo(a,2s+2) and Ro(a,2s+1), and has one output Bo(a,2s+2).

The stage (ring “b”, stage “t”) consists of 8 inputs namely Ri(b,2t+1), Ri(b,2t+2), Ui(b,2t+1), Ui(b,2t+2), J6, K6, L6, and M6; and 4 outputs Bo(b,2t+1), Bo(b,2t+2), Fo(b,2t+1), and Fo(b,2t+2). The stage (ring “b”, stage “t’) also consists of eight 2:1 Muxes namely R(b,2t+1), R(b,2t+2), F(b,2t+1), F(b,2t+2), U(b,2t+1), U(b,2t+2), B(b,2t+1), and B(b,2t+2). The 2:1 Mux R(b,2t+1) has two inputs namely Ri(b,2t+1) and J6, and has one output Ro(b,2t+1). The 2:1 Mux R(b,2t+2) has two inputs namely Ri(b,2t+2) and K6, and has one output Ro(b,2t+2). The 2:1 Mux F(b,2t+1) has two inputs namely Ro(b,2t+1) and Uo(b,2t+2), and has one output Fo(b,2t+1). The 2:1 Mux F(b,2t+2) has two inputs namely Ro(b,2t+2) and Uo(b,2t+1), and has one output Fo(b,2t+2).

The 2:1 Mux U(b,2t+1) has two inputs namely Ui(b,2t+1) and L6, and has one output Uo(b,2t+1). The 2:1 Mux U(b,2t+2) has two inputs namely Ui(b,2t+2) and M6, and has one output Uo(b,2t+2). The 2:1 Mux B(b,2t+1) has two inputs namely Uo(b,2t+1) and Ro(b,2t+2), and has one output Bo(b,2t+1). The 2:1 Mux B(b,2t+2) has two inputs namely Uo(b,2t+2) and Ro(b,2t+1), and has one output Bo(b,2t+2).

The wire Hop(1,1) starting from the output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is also connected to L5 of the stage (ring “a”, stage “s”), in addition to the input Ri(y,2q+4) of the stage (ring “y”, stage “q+1”). The stage (ring “x”, stage “p”), the stage (ring “a”, stage “s”), and the stage (ring “y”, stage “q+1”) may belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Therefore the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may not be equal to the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “y”, stage “q+1”). For example the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may be one where as the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “q”, stage “y+1”) may be two. In such a case the wire Hop(1,1) is called hereinafter a “multi-drop hop wire”. The wire Hop(1,1) may be either horizontal hop wire or vertical hop wire. Also multi-drop hop wires are either horizontal external hop wires or vertical external hop wires. Similarly the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may be any number greater than or equal to one, and also the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “q”, stage “y+1”) may be any number greater or equal to one.

In general a multi-drop hop wire may be dropping or terminating in more than one different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). For example a multi-drop hop wire starting from one block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) may be terminating at three different blocks or four different blocks, etc.

The wire Hop(1,2) starting from the output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is also connected to J6 of the stage (ring “b”, stage “t”), in addition to the input Ui(y,2q+2) of the stage (ring “y”, stage “q”). The wire Hop(1,2) is also an example of multi-drop hop wire when the stage (ring “x”, stage “p+1”), the stage (ring “b”, stage “t”) and the stage (ring “y”, stage “q”) belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The wire Hop(2,1) starting from the output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is also connected to M5 of the stage (ring “a”, stage “s”), in addition to the input Ri(x,2p+4) of the stage (ring “x”, stage “p+1”). The wire Hop(2,1) is also an example of multi-drop hop wire when the stage (ring “x”, stage “p+1”), the stage (ring “a”, stage “s”) and the stage (ring “y”, stage “q”) belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The wire Hop(2,2) starting from the output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is also connected to K6 of the stage (ring “b”, stage “t”), in addition to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”). The wire Hop(2,2) is also an example of multi-drop hop wire when the stage (ring “x”, stage “p”), the stage (ring “b”, stage “t”) and the stage (ring “y”, stage “q+1”) belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

In various embodiments, the inputs J5, K5, L5, and M5 are connected from any of the multi-drop hop wires starting from any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Also the inputs J6, K6, L6, and M6 are connected from any of the multi-drop hop wires starting from any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

The diagram 600A of FIG. 6A and 600B of FIG. 6B are different embodiments of all the connections with multi-drop hop wires, between multiple arbitrary stages in multiple different rings of different blocks of 2D-grid 800. Referring to diagram 600A in FIG. 6A illustrates all the connections with multi-drop hop wires, between an arbitrary stage of a ring namely the stages (ring “x”, stage “p”), and another arbitrary stage of any other ring namely the stages (ring “y”, stage “q”) of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). The multi-drop hop wires are also connected to another stage (ring “a”, stage “s”) belonging to a third block. The stage numbers x, y, p, q, a, and s all six are any whole numbers. In one embodiment p is equal to q and in another embodiment p is not equal to q. In another embodiment p is equal to q and p is equal to s. In yet another embodiment p, q and s all three are different. In general any combination of whole numbers for p, q, and s are possible.

The stage (ring “x”, stage “p”) consists of 8 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2), J1, K1, L1, and M1; and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of eight 2:1 Muxes namely R(x,2p+1), R(x,2p+2), F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux R(x,2p+1) has two inputs namely Ri(x,2p+1) and J1 and has one output Ro(x,2p+1). The 2:1 Mux R(x,2p+2) has two inputs namely Ri(x,2p+2) and K1 and has one output Ro(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Ro(x,2p+1) and Uo(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Ro(x,2p+2) and Uo(x,2p+1) and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and L1 and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and M1 and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Ro(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+2) and Ro(x,2p+1) and has one output Bo(x,2p+2).

The stage (ring “y”, stage “q”) consists of 8 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), Ui(y,2q+2), J3, K3, L3, and M3; and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of eight 2:1 Muxes namely R(y,2q+1), R(y,2q+2), F(y,2q+1), F(y,2q+2), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux R(y,2q+1) has two inputs namely Ri(y,2q+1) and J3 and has one output Ro(y,2q+1). The 2:1 Mux R(y,2q+2) has two inputs namely Ri(y,2q+2) and K3 and has one output Ro(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Ro(y,2q+1) and Uo(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Ro(y,2q+2) and Uo(y,2q+1) and has one output Fo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and L3, and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and M3, and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Ro(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+2) and Ro(y,2q+1) and has one output Bo(y,2q+2).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Ri(y,2q+2) of the stage (ring “y”, stage “q”). The output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(1,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

The wire Hop(1,1) starting from the output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is also connected to L2 of the stage (ring “a”, stage “s”), in addition to the input Ri(y,2q+2) of the stage (ring “y”, stage “q”). The stage (ring “x”, stage “p”), the stage (ring “a”, stage “s”), and the stage (ring “y”, stage “q”) may belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Therefore the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may not be equal to the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “y”, stage “q”). For example the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may be one where as the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “q”, stage “y”) may be two. Hence the wire Hop(1,1) is a multi-drop hop wire. Also the wire Hop(1,1) is either horizontal external hop wire or vertical external hop wire. Similarly the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may be any number greater than or equal to one, and also the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “q”, stage “y”) may be any number greater or equal to one.

The wire Hop(1,2) starting from the output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is also connected to K2 of the stage (ring “a”, stage “s”), in addition to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”). The wire Hop(1,2) is also an example of multi-drop hop wire when the stage (ring “x”, stage “p”), the stage (ring “a”, stage “s”) and the stage (ring “y”, stage “q”) belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

In various embodiments, the inputs J2, K2, L2, and M2 are connected from any of the multi-drop hop wires starting from any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

Referring to diagram 600B in FIG. 6B illustrates all the connections with multi-drop hop wires, between an arbitrary stage of a ring namely the stages (ring “x”, stage “p”), and another arbitrary stage of any other ring namely the stages (ring “y”, stage “q”) of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). The multi-drop hop wires are also connected to another stage (ring “a”, stage “s”) belonging to a third block. The stage numbers x, y, p, q, a, and s all six are any whole numbers. In one embodiment p is equal to q and in another embodiment p is not equal to q. In another embodiment p is equal to q and p is equal to s. In yet another embodiment p, q and s all three are different. In general any combination of whole numbers for p, q, and s are possible.

The stage (ring “x”, stage “p”) consists of 8 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2), J1, K1, L1, and M1; and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p’) also consists of four 4:1 Muxes namely F(x,2p+1), F(x,2p+2), B(x,2p+1), and B(x,2p+2). The 4:1 Mux F(x,2p+1) has four inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+2), and J1 and has one output Fo(x,2p+1). The 4:1 Mux F(x,2p+2) has four inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), and K1 and has one output Fo(x,2p+2).

The 4:1 Mux B(x,2p+1) has four inputs namely Ui(x,2p+1), Ui(x,2p+2), Ri(x,2p+2), and L1 and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Ui(x,2p+1), Ui(x,2p+2), Ri(x,2p+1), and M1 and has one output Bo(x,2p+2).

The stage (ring “y”, stage “q”) consists of 8 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), Ui(y,2q+2), J3, K3, L3, and M3; and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q’) also consists of four 4:1 Muxes namely F(y,2q+1), F(y,2q+2), B(y,2q+1), and B(y,2q+2). The 4:1 Mux F(y,2q+1) has four inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+2), and J3 and has one output Fo(y,2q+1). The 4:1 Mux F(y,2q+2) has four inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), and K3 and has one output Fo(y,2q+2).

The 4:1 Mux B(y,2q+1) has four inputs namely Ui(y,2q+1), Ui(y,2q+2), Ri(y,2q+2), and L3, and has one output Bo(y,2q+1). The 4:1 Mux B(y,2q+2) has four inputs namely Ui(y,2q+1), Ui(y,2q+2), Ri(y,2q+1), and M3, and has one output Bo(y,2q+2).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to the input Ri(y,2q+2) of the stage (ring “y”, stage “q”). The output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(1,2) to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”).

The wire Hop(1,1) starting from the output Fo(x,2p+2) of the stage (ring “x” stage “p”) is also connected to L2 and J2 of the stage (ring “a”, stage “s”), in addition to the input Ri(y,2q+2) of the stage (ring “y”, stage “q”). The stage (ring “x”, stage “p”), the stage (ring “a”, stage “s”), and the stage (ring “y”, stage “q”) may belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s). Therefore the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may not be equal to the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “y”, stage “q”). For example the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may be one where as the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “q”, stage “y”) may be two. Hence the wire Hop(1,1) is a multi-drop hop wire. Also the wire Hop(1,1) is either horizontal external hop wire or vertical external hop wire. Similarly the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “a”, stage “s”) may be any number greater than or equal to one, and also the hop length between the blocks consisting of the stage (ring “x”, stage “p”) and the stage (ring “q”, stage “y”) may be any number greater or equal to one.

The wire Hop(1,2) starting from the output Bo(y,2q+2) of the stage (ring “y”, stage “q”) is also connected to K2 and M2 of the stage (ring “a”, stage “s”), in addition to the input Ui(x,2p+2) of the stage (ring “x”, stage “p”). The wire Hop(1,2) is also an example of multi-drop hop wire when the stage (ring “x”, stage “p”), the stage (ring “a”, stage “s”) and the stage (ring “y”, stage “q”) belong to three different blocks of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

In various embodiments, the inputs J2, K2, L2, and M2 are connected from any of the multi-drop hop wires starting from any other stages of any ring of any block of the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s).

Referring to diagram 700A in FIG. 7A, illustrates, in one embodiment, the hop wire connections chart of a partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A or a partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B, or a partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C, with m=6 and n=7. The hop wire connections chart shows two rings namely ring 1 and ring 2. And there are m+1=7 stages in ring 1 and n+1=8 stages in ring 2.

The hop wire connections chart 700A illustrates how the hop wires are connected between any two successive stages of all the rings corresponding to a block of 2D-grid 800. “Lx” denotes an internal hop wire connection, where symbol “L” denotes internal hop wire and “x” is an integer. For example “L1” between the stages (ring 1, stage 0) and (ring 1, stage 1) denotes that the corresponding hop wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are connected to two successive stages of another ring in the same block or alternatively hop wires Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) are internal hop wires. Since there is also “L1” between the stages (ring 2, stage 0) and (ring 2, stage 1), there are internal hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) connected between the stages (ring 1, stage 0) and (ring 1, stage 1) and the stages (ring 2, stage 0) and (ring 2, stage 1). Hence there can be only two “L1” labels in the hop wire connection chart 700A.

Similarly there are two “L2” labels in the hop wire connections chart 700A. Since the label “L2” is given between the stages (ring 1, stage 5) and (ring 1, stage 6) and also the label “L2” is given between the stages (ring 2, stage 3) and (ring 2, stage 4), there are corresponding internal hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) connected between the stages (ring 1, stage 5) and (ring 1, stage 6) and the stages (ring 2, stage 3) and (ring 2, stage 4).

“Vx” denotes an external vertical hop wire, where symbol “V” denotes vertical external hop wire connections from blocks of the topmost row of 2D-grid 800 (i.e., row of blocks consisting of block (1,1), block (1,2), . . . , and block (1,10)) to the same corresponding stages of the same numbered ring of another block that is directly down south, with “x” vertical hop length, where “x” is a positive integer. For example “V1” between the stages (ring 1, stage 1) and (ring 1, stage 2) denote that from block (1,1) of 2D-grid 800 to another block directly below it, which is block (2,1), since “V1” denotes hop length of 1, there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 1) and (ring 1, stage 2) of block (1,1) to (ring 1, stage 1) and (ring 1, stage 2) of block (2,1). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 1) and (ring 1, stage 2) of block (3,1) to (ring 1, stage 1) and (ring 1, stage 2) of block (4,1). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 1) and (ring 1, stage 2) of block (9,1) to (ring 1, stage 1) and (ring 1, stage 2) of block (10,1). The same pattern continues for all the columns starting from the block in the topmost row of each column.

Similarly “V3” between the stages (ring 2, stage 1) and (ring 2, stage 2) denote that from block (1,1) of 2D-grid 800 to another block below it and at a hop length of 3 which is block (4,1), there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 1) and (ring 2, stage 2) of block (1,1) to (ring 2, stage 1) and (ring 2, stage 2) of block (4,1). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 1) and (ring 2, stage 2) of block (2,1) to (ring 2, stage 1) and (ring 2, stage 2) of block (5,1). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 1) and (ring 2, stage 2) of block (7,1) to (ring 2, stage 1) and (ring 2, stage 2) of block (10,1). The same pattern continues for all the columns starting from the block in the topmost row of each column.

If there is no block that is directly below a block with hop length equal to 3 then there is no vertical external hop wire connections is given corresponding to those two successive stages of the blocks. For example block (8,1) does not have any block that is directly below and with hop length equal to 3 then none of the vertical external hop wires are connected from (ring 2, stage 1) and (ring 2, stage 2) of block (8,1). Similarly from (ring 2, stage 1) and (ring 2, stage 2) of block (9,1) and from (ring 2, stage 1) and (ring 2, stage 2) of block (10,1), none of the vertical external hop wires are connected. Similarly vertical external hop wires are connected corresponding to “V5”, “V7” etc., labels given in the hop wire connections chart 700A.

“Ux” denotes an external vertical hop wire, where symbol “U” denotes vertical external hop wire connections starting from blocks that are “x” hop length below the topmost row of 2D-grid 800 (i.e., row of blocks consisting of block (1+x,1), block (1+x,2), . . . , and block (1+x,10)) to the same corresponding stages of the same numbered ring of another block that is directly down below, with “x” vertical hop length, where “x” is a positive integer. For example “U1” between the stages (ring 1, stage 2) and (ring 1, stage 3) denote that from block (2,1) of 2D-grid 800 to another block directly below it, which is block (3,1), since “U1” denotes hop length of 1, there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 2) and (ring 1, stage 3) of block (2,1) to (ring 1, stage 2) and (ring 1, stage 3) of block (3,1). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 2) and (ring 1, stage 3) of block (4,1) to (ring 1, stage 2) and (ring 1, stage 3) of block (5,1). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 2) and (ring 1, stage 3) of block (8,1) to (ring 1, stage 2) and (ring 1, stage 3) of block (9,1). The same pattern continues for all the columns starting from the block in the topmost row of each column.

If there is no block that is directly below a block with hop length equal to 1 then no vertical external hop wire connections is given corresponding to those two successive stages of the blocks. For example block (10,1) does not have any block that is directly below and with hop length equal to 1 then none of the vertical external hop wires are connected from (ring 1, stage 2) and (ring 1, stage 3) of block (10,1). Similarly for all the blocks in each column from the topmost row up to the row “x”, no vertical external hop wires are connected to the corresponding (ring 1, stage 2) and (ring 1, stage 3).

Similarly “U3” between the stages (ring 2, stage 2) and (ring 2, stage 3) denote that starting from blocks that are 3 hop length below the topmost row of 2D-grid 800 (i.e., row of blocks consisting of block (4,1), block (4,2), . . . , and block (4,10)) to the same corresponding stages of the same numbered ring of another block that is directly down below, with vertical hop length of 3, there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) connected. For example from block (4,1) of 2D-grid 800 to another block below it and at a hop length of 3 which is block (7,1), there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 2) and (ring 2, stage 3) of block (4,1) to (ring 2, stage 1) and (ring 2, stage 2) of block (7,1). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 2) and (ring 2, stage 3) of block (5,1) to (ring 2, stage 2) and (ring 2, stage 3) of block (8,1). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 2) and (ring 2, stage 3) of block (7,1) to (ring 2, stage 2) and (ring 2, stage 3) of block (10,1). The same pattern continues for all the columns starting from the block in the topmost row of each column.

If there is no block that is directly below a block with hop length equal to 3 then no vertical external hop wire connections is given corresponding to those two successive stages of the blocks. For example block (8,1) does not have any block that is directly below and with hop length equal to 3 then none of the vertical external hop wires are connected from (ring 2, stage 2) and (ring 2, stage 3) of block (8,1). Similarly from (ring 2, stage 2) and (ring 2, stage 3) of block (9,1) and from (ring 2, stage 2) and (ring 2, stage 3) of block (10,1), none of the vertical external hop wires are connected. Similarly vertical external hop wires are connected corresponding to “U5”, “U7” etc. labels given in the hop wire connections chart 700A.

“Hx” denotes an external horizontal hop wire, where symbol “H” denotes horizontal external hop wire connections from blocks of the leftmost column of 2D-grid 800 (i.e., column of blocks consisting of block (1,1), block (2,1), . . . , and block (10,1)) to the same corresponding stages of the same numbered ring of another block that is directly to the right, with “x” horizontal hop length, where “x” is a positive integer. For example “H1” between the stages (ring 1, stage 3) and (ring 1, stage 4) denote that from block (1,1) of 2D-grid 800 to another block directly to the right, which is block (1,2), since “H1” denotes hop length of 1, there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 3) and (ring 1, stage 4) of block (1,1) to (ring 1, stage 3) and (ring 1, stage 4) of block (1,2). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 3) and (ring 1, stage 4) of block (1,3) to (ring 1, stage 3) and (ring 1, stage 4) of block (1,4). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 3) and (ring 1, stage 4) of block (9,1) to (ring 1, stage 3) and (ring 1, stage 4) of block (10,1). The same pattern continues for all the rows starting from the block in the leftmost block of each row.

Similarly “H3” between the stages (ring 2, stage 4) and (ring 2, stage 5) denote that from block (1,1) of 2D-grid 800 to another block to the right and at a hop length of 3 which is block (1,4), there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 4) and (ring 2, stage 5) of block (1,1) to (ring 2, stage 4) and (ring 2, stage 5) of block (1,4). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 4) and (ring 2, stage 5) of block (1,2) to (ring 2, stage 4) and (ring 2, stage 5) of block (1,5). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 4) and (ring 2, stage 5) of block (1,7) to (ring 2, stage 4) and (ring 2, stage 5) of block (1,10). The same pattern continues for all the columns starting from the block in the leftmost column of each row.

If there is no block that is directly to the right with hop length equal to 3 then there is no horizontal external hop wire connections is given corresponding to those two successive stages of the blocks. For example block (1,8) does not have any block that is directly to the right and with hop length equal to 3 then none of the horizontal external hop wires are connected from (ring 2, stage 4) and (ring 2, stage 5) of block (1,8). Similarly from (ring 2, stage 4) and (ring 2, stage 5) of block (1,9) and from (ring 2, stage 4) and (ring 2, stage 5) of block (1,10), none of the horizontal external hop wires are connected. Similarly horizontal external hop wires are connected corresponding to “H5”, “H7” etc., labels given in the hop wire connections chart 700A.

“Kx” denotes an external horizontal hop wire, where symbol “K” denotes horizontal external hop wire connections starting from blocks that are “x” hop length below the leftmost column of 2D-grid 800 (i.e., column of blocks consisting of block (1, 1+x), block (2, 1+x), . . . , and block (10, 1+x)) to the same corresponding stages of the same numbered ring of another block that is directly to the right, with “x” horizontal hop length, where “x” is a positive integer. For example “K1” between the stages (ring 1, stage 4) and (ring 1, stage 5) denote that from block (1,2) of 2D-grid 800 to another block directly to the right, which is block (1,3), since “K1” denotes hop length of 1, there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 4) and (ring 1, stage 5) of block (1,2) to (ring 1, stage 4) and (ring 1, stage 5) of block (1,3). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 4) and (ring 1, stage 4) of block (1,4) to (ring 1, stage 4) and (ring 1, stage 5) of block (1,5). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 1, stage 4) and (ring 1, stage 5) of block (1,8) to (ring 1, stage 4) and (ring 1, stage 5) of block (1,9). The same pattern continues for all the rows starting from the block in the leftmost column of each row.

If there is no block that is directly to the right of a block with hop length equal to 1 then no horizontal external hop wire connections is given corresponding to those two successive stages of the blocks. For example block (1,10) does not have any block that is directly to the right and with hop length equal to 1 then none of the horizontal external hop wires are connected from (ring 1, stage 4) and (ring 1, stage 5) of block (1,10). Similarly for all the blocks in each row from the leftmost column up to the column “x”, no horizontal external hop wires are connected to the corresponding (ring 1, stage 4) and (ring 1, stage 5).

Similarly “K3” between the stages (ring 2, stage 5) and (ring 2, stage 6) denote that starting from blocks that are 3 hop length to the right of the leftmost column of 2D-grid 800 (i.e., column of blocks consisting of block (1,4), block (2,4), . . . , and block (10,4)) to the same corresponding stages of the same numbered ring of another block that is directly to the right, with horizontal hop length of 3, there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) connected. For example from block (1,4) of 2D-grid 800 to another block to the right and at a hop length of 3 which is block (1,7), there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 5) and (ring 2, stage 6) of block (1,4) to (ring 2, stage 5) and (ring 2, stage 6) of block (1,7). It also means there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 5) and (ring 2, stage 6) of block (1,5) to (ring 2, stage 5) and (ring 2, stage 6) of block (1,8). This pattern continues and finally there are external hop wire connections Hop(1,1), Hop(1,2), Hop(2,1), and Hop(2,2) from (ring 2, stage 5) and (ring 2, stage 6) of block (1,7) to (ring 2, stage 5) and (ring 2, stage 6) of block (1,10). The same pattern continues for all the rows starting from the block in the leftmost block of each row.

If there is no block that is directly to the right of a block with hop length equal to 3 then no horizontal external hop wire connections is given corresponding to those two successive stages of the blocks. For example block (1,8) does not have any block that is directly to the right and with hop length equal to 3 then none of the horizontal external hop wires are connected from (ring 2, stage 5) and (ring 2, stage 6) of block (1,8). Similarly from (ring 2, stage 5) and (ring 2, stage 6) of block (1,9) and from (ring 2, stage 5) and (ring 2, stage 6) of block (1,10), none of the horizontal external hop wires are connected. Similarly horizontal external hop wires are connected corresponding to “K5”, “K7” etc. labels given in the hop wire connections chart 700A.

In general the hop length of an external vertical hop wire can be any positive number. Similarly the hop length of an external horizontal hop wire can be any positive number. The hop wire connections between two arbitrary successive stages in two different rings of the same block or two different rings of different blocks described in diagram 700A of FIG. 7A may be any one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, and 300E of FIG. 3E. Similarly the multi-drop hop wire connections between two arbitrary successive stages in two different rings of different blocks described in diagram 700A of FIG. 7A may be any one of the embodiments of either the diagrams 500A of FIG. 5A.

In accordance with the invention, the hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may also be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, and 400D of FIG. 4D. Similarly the multi-drop hop wire connections between two arbitrary stages in two different rings of different blocks may also be any one of the embodiments of either the diagrams 600A of FIG. 6A or 600B of FIG. 6B. Also in an embodiment all the connections between two stages of two rings may all are between the same numbered stages or same level stages. Particularly in embodiments for FPGA's external hop wires are cascaded for the signal to travel in a direction for a long hop length which requires all embodiments of the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, and 400D of FIG. 4D are implemented with connection between the same numbered stages or same level stages.

Similarly in embodiments for FPGA's external hop wires are cascaded for the signal to travel in a direction for a long hop length which requires multi-hop wire embodiments of the diagrams 600A of FIG. 6A or 600B of FIG. 6B.are implemented with connections between the same numbered stages or same level stages at one or all of the drop stages multi-drop hop wires.

In another embodiment some of the connections may be between the same numbered stages or same level stages and some other connections may be between the different numbered stages or different level stages. Numerous embodiments are disclosed with each embodiment having one or more benefits over other embodiments.

In accordance with the current invention, either partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100A of FIG. 1A or partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100B of FIG. 1B, or partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100C of FIG. 1C, or one or more slices of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D of FIG. 1D corresponding to a block of 2D-grid of blocks 800 of FIG. 8, using any one of the embodiments of 200A-200E of FIGS. 2A-2E to implement a stage of a ring of the multi-stage pyramid network, either by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks described in diagram 700A of FIG. 7A may be any one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B is very efficient in the reduction of the die size, power consumption, and for lower wire/path delay for higher performance for practical routing applications to particularly to set up broadcast, unicast and multicast connections. In general in accordance with the current invention, where N₁ and N₂ of the complete multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) may be arbitrarily large in size and also the 2D-grid size 800 may also be arbitrarily large in size in terms of both the number of rows and number of columns.

Delay Optimizations in Multi-Stage Pyramid Network V_(D-Comb)(N₁,N₂,d,s):

The multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) according to the current invention can further be optimized to reduce the delay in the routed path of the connection. The delay optimized multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) is hereinafter denoted by V_(D-Comb)(N₁,N₂,d,s). The delay optimizing embodiments of the stages of a ring are one of the diagrams namely 900A-900E of FIGS. 9A-9D, 1000A-1000F of FIGS. 10A-10F, and 1100A-1100C of FIGS. 11A-11C. The diagram 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 are different embodiments for the implementation of delay optimizations with all the connections between two arbitrary successive stages in two different rings of the same block or two different rings of different blocks of 2D-grid 800.

FIG. 9A illustrates a stage (ring “k”, stage “m”) 900A consists of 5 inputs namely Fi(k,2m+1), Fi(k,2m+2), YFi(k,2m+1), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of seven 2:1 Muxes namely YF(k,2m+1), F(k,2m+1), F(k,2m+2), U(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The 2:1 Mux YF(k,2m+1) has two inputs namely Fi(k,2m+1) and YFi(k,2m+1) and has one output YFo(k,2m+1). The 2:1 Mux F(k,2m+1) has two inputs namely YFo(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely YFo(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 9B illustrates a stage (ring “k”, stage “m”) 900B consists of 5 inputs namely Fi(k,2m+1), Fi(k,2m+2), YUi(k,2m+1), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of seven 2:1 Muxes namely F(k,2m+1), F(k,2m+2), YF(k,2m+1), U(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux YU(k,2m+1) has two inputs namely Ui(k,2m+1) and YUi(k,2m+1) and has one output YUo(k,2m+1). The 2:1 Mux U(k,2m+1) has two inputs namely YUo(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 9C illustrates a stage (ring “k”, stage “m”) 900C consists of 5 inputs namely Fi(k,2m+1), Fi(k,2m+2), UYi(k,2m+1), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of five 2:1 Muxes namely F(k,2m+1), F(k,2m+2), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The stage (ring “k”, stage “m”) also consists of one 3:1 Mux namely UY(k,2m+1). The 2:1 Mux F(k,2m+1) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Fi(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2).

The 3:1 Mux UY(k,2m+1) has three inputs namely Ui(k,2m+1), UYi(k,2m+1) and Fo(k,2m+1) and has one output UYo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 9D illustrates a stage (ring “k”, stage “m”) 900D consists of 6 inputs namely Fi(k,2m+1), Fi(k,2m+2), YFi(k,2m+1), Ui(k,2m+1), Ui(k,2m+2), and YUi(k,2m+1); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of eight 2:1 Muxes namely F(k,2m+1), F(k,2m+2), YF(k,2m+1), U(k,2m+1), U(k,2m+2), YU(k,2m+1), B(k,2m+1), and B(k,2m+2). The 2:1 Mux YF(k,2m+1) has two inputs namely Fi(k,2m+1) and YFi(k,2m+1) and has one output YFo(k,2m+1). The 2:1 Mux F(k,2m+1) has two inputs namely YFo(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely YFo(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux YU(k,2m+1) has two inputs namely Ui(k,2m+1) and YUi(k,2m+1) and has one output YUo(k,2m+1). The 2:1 Mux U(k,2m+1) has two inputs namely YUo(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 9E illustrates a stage (ring “k”, stage “m”) 900E consists of 6 inputs namely Fi(k,2m+1), Fi(k,2m+2), YFi(k,2m+1), Ui(k,2m+1), Ui(k,2m+2), and UYi(k,2m+1); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of six 2:1 Muxes namely F(k,2m+1), F(k,2m+2), YF(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The stage (ring “k”, stage “m”) also consists of one 3:1 Mux namely UY(k,2m+1). The 2:1 Mux YF(k,2m+1) has two inputs namely Fi(k,2m+1) and YFi(k,2m+1) and has one output YFo(k,2m+1). The 2:1 Mux F(k,2m+1) has two inputs namely YFo(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely YFo(k,2m+1) and Fi(k,2m+2) and has one output Fo(k,2m+2).

The 3:1 Mux UY(k,2m+1) has three inputs namely Ui(k,2m+1), UYi(k,2m+1) and Fo(k,2m+1) and has one output UYo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 10A illustrates a stage (ring “k”, stage “m”) 1000A consists of 5 inputs namely Ri(k,2m+1), Ri(k,2m+2), YRi(k,2m+1), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of nine 2:1 Muxes namely R(k,2m+1), R(k,2m+2), YR(k,2m+1), F(k,2m+1), F(k,2m+2), U(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The 2:1 Mux YR(k,2m+1) has two inputs namely Ri(k,2m+1) and YRi(k,2m+1) and has one output YRo(k,2m+1). The 2:1 Mux R(k,2m+1) has two inputs namely YRo(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 10B illustrates a stage (ring “k”, stage “m”) 1000B consists of 5 inputs namely Ri(k,2m+1), Ri(k,2m+2), RYi(k,2m+1), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of seven 2:1 Muxes namely R(k,2m+2), F(k,2m+1), F(k,2m+2), U(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The stage (ring “k”, stage “m”) also consists of one 3:1 Mux namely RY(k,2m+1). The 3:1 Mux RY(k,2m+1) has three inputs namely Ri(k,2m+1), RYi(k,2m+1), and Bo(k,2m+1), and has one output RYo(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely RYo(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely RYo(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 10C illustrates a stage (ring “k”, stage “m”) 1000C consists of 5 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), Ui(k,2m+2), and YUi(k,2m+1); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of nine 2:1 Muxes namely R(k,2m+1), R(k,2m+2), F(k,2m+1), F(k,2m+2), YU(k,2m+1), U(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux YU(k,2m+1) has two inputs namely Ui(k,2m+1) and YUi(k,2m+1) and has one output YUo(k,2m+1). The 2:1 Mux U(k,2m+1) has two inputs namely YUo(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 10D illustrates a stage (ring “k”, stage “m”) 1000D consists of 5 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), Ui(k,2m+2), and UYi(k,2m+1); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of seven 2:1 Muxes namely R(k,2m+1), R(k,2m+2), F(k,2m+1), F(k,2m+2), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The stage (ring “k”, stage “m”) also consists of one 3:1 Mux namely UY(k,2m+1). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+2).

The 3:1 Mux UY(k,2m+1) has three inputs namely Ui(k,2m+1), UYi(k,2m+1), and Fo(k,2m+1), and has one output UYo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 10E illustrates a stage (ring “k”, stage “m”) 1000E consists of 6 inputs namely Ri(k,2m+1), Ri(k,2m+2), YRi(k,2m+1), Ui(k,2m+1), Ui(k,2m+2), and YUi(k,2m+1); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of ten 2:1 Muxes namely YR(k,2m+1), R(k,2m+1), R(k,2m+2), F(k,2m+1), F(k,2m+2), YU(k,2m+1), U(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The 2:1 Mux YR(k,2m+1) has two inputs namely Ri(k,2m+1) and YRi(k,2m+1) and has one output YRo(k,2m+1). The 2:1 Mux R(k,2m+1) has two inputs namely YRo(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+2).

The 2:1 Mux YU(k,2m+1) has two inputs namely Ui(k,2m+1) and YUi(k,2m+1) and has one output YUo(k,2m+1). The 2:1 Mux U(k,2m+1) has two inputs namely YUo(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 10F illustrates a stage (ring “k”, stage “m”) 1000F consists of 6 inputs namely Ri(k,2m+1), Ri(k,2m+2), RYi(k,2m+1), Ui(k,2m+1), Ui(k,2m+2), and UYi(k,2m+1); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of six 2:1 Muxes namely R(k,2m+2), F(k,2m+1), F(k,2m+2), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The stage (ring “k”, stage “m”) also consists of two 3:1 Mux namely RY(k,2m+1) and UY(k,2m+1). The 3:1 Mux RY(k,2m+1) has three inputs namely Ri(k,2m+1), RYi(k,2m+1), and Bo(k,2m+1) and has one output RYo(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely RYo(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely RYo(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+2).

The 3:1 Mux UY(k,2m+1) has three inputs namely Ui(k,2m+1), UYi(k,2m+1), and Fo(k,2m+1), and has one output UYo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely UYo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 11A illustrates a stage (ring “k”, stage “m”) 1100A consists of 5 inputs namely Ri(k,2m+1), Ri(k,2m+2), FYi(k,2m+2), Ui(k,2m+1), and Ui(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of seven 2:1 Muxes namely R(k,2m+1), R(k,2m+2), F(k,2m+1), U(k,2m+1), U(k,2m+2), B(k,2m+1), and B(k,2m+2). The stage (ring “k”, stage “m”) also consists of one 3:1 Mux namely FY(k,2m+2). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 3:1 Mux FY(k,2m+2) has three inputs namely Ro(k,2m+1), Ro(k,2m+2), and FYi(k,2m+2), and has one output FYo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and FYo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 2:1 Mux B(k,2m+2) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+2).

FIG. 11B illustrates a stage (ring “k”, stage “m”) 1100B consists of 5 inputs namely Ri(k,2m+1), Ri(k,2m+2), Ui(k,2m+1), Ui(k,2m+2), and BYi(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of seven 2:1 Muxes namely R(k,2m+1), R(k,2m+2), F(k,2m+1), F(k,2m+2), U(k,2m+1), U(k,2m+2), and B(k,2m+1). The stage (ring “k”, stage “m”) also consists of one 3:1 Mux namely BY(k,2m+2). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 2:1 Mux F(k,2m+2) has two inputs namely Ro(k,2m+1), and Ro(k,2m+2), and has one output Fo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and Fo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 3:1 Mux BY(k,2m+2) has three inputs namely Uo(k,2m+1), Uo(k,2m+2), and BYi(k,2m+2), and has one output BYo(k,2m+2).

FIG. 11C illustrates a stage (ring “k”, stage “m”) 1100C consists of 6 inputs namely Ri(k,2m+1), Ri(k,2m+2), FYi(k,2m+2), Ui(k,2m+1), Ui(k,2m+2), and BYi(k,2m+2); and 4 outputs Bo(k,2m+1), Bo(k,2m+2), Fo(k,2m+1), and Fo(k,2m+2). The stage (ring “k”, stage “m”) also consists of six 2:1 Muxes namely R(k,2m+1), R(k,2m+2), F(k,2m+1), U(k,2m+1), U(k,2m+2), and B(k,2m+1). The stage (ring “k”, stage “m”) also consists of two 3:1 Muxes namely FY(k,2m+2) and BY(k,2m+2). The 2:1 Mux R(k,2m+1) has two inputs namely Ri(k,2m+1) and Bo(k,2m+1) and has one output Ro(k,2m+1). The 2:1 Mux R(k,2m+2) has two inputs namely Ri(k,2m+2) and Bo(k,2m+2) and has one output Ro(k,2m+2). The 2:1 Mux F(k,2m+1) has two inputs namely Ro(k,2m+1) and Ro(k,2m+2) and has one output Fo(k,2m+1). The 3:1 Mux FY(k,2m+2) has three inputs namely Ro(k,2m+1), Ro(k,2m+2), and FYi(k,2m+2), and has one output FYo(k,2m+2).

The 2:1 Mux U(k,2m+1) has two inputs namely Ui(k,2m+1) and Fo(k,2m+1) and has one output Uo(k,2m+1). The 2:1 Mux U(k,2m+2) has two inputs namely Ui(k,2m+2) and FYo(k,2m+2) and has one output Uo(k,2m+2). The 2:1 Mux B(k,2m+1) has two inputs namely Uo(k,2m+1) and Uo(k,2m+2) and has one output Bo(k,2m+1). The 3:1 Mux BY(k,2m+2) has three inputs namely Uo(k,2m+1), Uo(k,2m+2), and BYi(k,2m+2) and has one output BYo(k,2m+2).

Referring to diagram 1200 in FIG. 12, illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 5 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2), and UYi(x,2p+1); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p”) also consists of seven 2:1 Muxes namely R(x,2p+1), R(x,2p+2), F(x,2p+1), F(x,2p+2), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The stage (ring “x”, stage “p”) also consists of one 3:1 Mux namely UY(x,2p+1). The 2:1 Mux R(x,2p+1) has two inputs namely Ri(x,2p+1) and Bo(x,2p+1) and has one output Ro(x,2p+1). The 2:1 Mux R(x,2p+2) has two inputs namely Ri(x,2p+2) and Bo(x,2p+2) and has one output Ro(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Ro(x,2p+1) and Ro(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Ro(x,2p+1) and Ro(x,2p+2) and has one output Fo(x,2p+2).

The 3:1 Mux UY(x,2p+1) has three inputs namely Ui(x,2p+1), UYi(x,2p+1), and Fo(x,2p+1), and has one output UYo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely UYo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely UYo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 5 inputs namely Ri(x,2p+3), Ri(x,2p+4), RYi(x,2p+3), Ui(x,2p+3), and Ui(x,2p+4); and 4 outputs Bo(x,2p+3), Bo(x,2p+4), Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of seven 2:1 Muxes namely R(x,2p+4), F(x,2p+3), F(x,2p+4), U(x,2p+3), U(x,2p+4), B(x,2p+3), and B(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of one 3:1 Mux namely RY(x,2p+3). The 3:1 Mux RY(x,2p+3) has three inputs namely Ri(x,2p+3), RYi(x,2p+3), and Bo(x,2p+3), and has one output RYo(x,2p+3). The 2:1 Mux R(x,2p+4) has two inputs namely Ri(x,2p+4) and Bo(x,2p+4) and has one output Ro(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely RYo(x,2p+3) and Ro(x,2p+4) and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely RYo(x,2p+3) and Ro(x,2p+4) and has one output Fo(x,2p+4).

The 2:1 Mux U(x,2p+3) has two inputs namely Ui(x,2p+3) and Fo(x,2p+3) and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Ui(x,2p+4) and Fo(x,2p+4) and has one output Uo(x,2p+4). The 2:1 Mux B(x,2p+3) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Ri(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Bo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 5 inputs namely Ri(y,2q+1), Ri(y,2q+2), Ui(y,2q+1), Ui(y,2q+2), and YUi(y,2q+1); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q”) also consists of nine 2:1 Muxes namely R(y,2q+1), R(y,2q+2), F(y,2q+1), F(y,2q+2), YU(y,2q+1), U(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The 2:1 Mux R(y,2q+1) has two inputs namely Ri(y,2q+1) and Bo(y,2q+1) and has one output Ro(y,2q+1). The 2:1 Mux R(y,2q+2) has two inputs namely Ri(y,2q+2) and Bo(y,2q+2) and has one output Ro(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Ro(y,2q+1) and Ro(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Ro(y,2q+1) and Ro(y,2q+2) and has one output Fo(y,2q+2).

The 2:1 Mux YU(y,2q+1) has two inputs namely Ui(y,2q+1) and YUi(y,2q+1) and has one output YUo(y,2q+1). The 2:1 Mux U(y,2q+1) has two inputs namely YUo(y,2q+1) and Fo(y,2q+1) and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 5 inputs namely Ri(y,2q+3), Ri(y,2q+4), YRi(y,2q+3), Ui(y,2q+3), and Ui(y,2q+4); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of nine 2:1 Muxes namely R(y,2q+3), R(y,2q+4), YR(y,2q+3), F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux YR(y,2q+3) has two inputs namely Ri(y,2q+3) and YRi(y,2q+3) and has one output YRo(y,2q+3). The 2:1 Mux R(y,2q+3) has two inputs namely YRo(y,2q+3) and Bo(y,2q+3) and has one output Ro(y,2q+3). The 2:1 Mux R(y,2q+4) has two inputs namely Ri(y,2q+4) and Bo(y,2q+4) and has one output Ro(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely Ro(y,2q+3) and Ro(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely Ro(y,2q+3) and Ro(y,2q+4) and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and Fo(y,2q+3) and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Ri(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to two inputs namely input Ri(y,2q+4) of the stage (ring “y”, stage “q+1”) and input YUi(y,2q+1) of the stage (ring “y”, stage “q”). The output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to two inputs namely input Ui(y,2q+2) of the stage (ring “y”, stage “q”) and input YRi(y,2q+3) of the stage (ring “y”, stage “q+1”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to two inputs namely input Ri(x,2p+4) of the stage (ring “x”, stage “p+1”) and input UYi(x,2p+1) of the stage (ring “x”, stage “p”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to two inputs namely input Ui(x,2p+2) of the stage (ring “x”, stage “p”) and input RYi(x,2p+3) of the stage (ring “x”, stage “p+1”).

Referring to diagram 1300 in FIG. 13, illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 6 inputs namely Fi(x,2p+1), Fi(x,2p+2), YFi(x,2p+1), Ui(x,2p+1), Ui(x,2p+2), and YUi(x,2p+1); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p”) also consists of eight 2:1 Muxes namely F(x,2p+1), F(x,2p+2), YF(x,2p+1), U(x,2p+1), U(x,2p+2), YU(x,2p+1), B(x,2p+1), and B(x,2p+2). The 2:1 Mux YF(x,2p+1) has two inputs namely Fi(x,2p+1) and YFi(x,2p+1) and has one output YFo(x,2p+1). The 2:1 Mux F(x,2p+1) has two inputs namely YFo(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely YFo(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+2).

The 2:1 Mux YU(x,2p+1) has two inputs namely Ui(x,2p+1) and YUi(x,2p+1) and has one output YUo(x,2p+1). The 2:1 Mux U(x,2p+1) has two inputs namely YUo(x,2p+1) and Fo(x,2p+1) and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 6 inputs namely Ri(x,2p+3), Ri(x,2p+4), YRi(x,2p+3), Ui(x,2p+3), Ui(x,2p+4), and YUi(x,2p+3); and 4 outputs Bo(x,2p+3), Bo(x,2p+4), Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of ten 2:1 Muxes namely YR(x,2p+3), R(x,2p+3), R(x,2p+4), F(x,2p+3), F(x,2p+4), YU(x,2p+3), U(x,2p+3), U(x,2p+4), B(x,2p+3), and B(x,2p+4). The 2:1 Mux YR(x,2p+3) has two inputs namely Ri(x,2p+3) and YRi(x,2p+3) and has one output YRo(x,2p+3). The 2:1 Mux R(x,2p+3) has two inputs namely YRo(x,2p+3) and Bo(x,2p+3) and has one output Ro(x,2p+3). The 2:1 Mux R(x,2p+4) has two inputs namely Ri(x,2p+4) and Bo(x,2p+4) and has one output Ro(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely Ro(x,2p+3) and Ro(x,2p+4) and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely Ro(x,2p+3) and Ro(x,2p+4) and has one output Fo(x,2p+4).

The 2:1 Mux YU(x,2p+3) has two inputs namely Ui(x,2p+3) and YUi(x,2p+3) and has one output YUo(x,2p+3). The 2:1 Mux U(x,2p+3) has two inputs namely YUo(x,2p+3) and Fo(x,2p+3) and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Ui(x,2p+4) and Fo(x,2p+4) and has one output Uo(x,2p+4). The 2:1 Mux B(x,2p+3) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Ri(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Bo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 6 inputs namely Fi(y,2q+1), Fi(y,2q+2), YFi(y,2q+1), Ui(y,2q+1), Ui(y,2q+2), and UYi(y,2q+1); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q”) also consists of six 2:1 Muxes namely F(y,2q+1), F(y,2q+2), YF(y,2q+1), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The stage (ring “y”, stage “q”) also consists of one 3:1 Mux namely UY(y,2q+1). The 2:1 Mux YF(y,2q+1) has two inputs namely Fi(y,2q+1) and YFi(y,2q+1) and has one output YFo(y,2q+1). The 2:1 Mux F(y,2q+1) has two inputs namely YFo(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely YFo(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+2).

The 3:1 Mux UY(y,2q+1) has three inputs namely Ui(y,2q+1), UYi(y,2q+1) and Fo(y,2q+1) and has one output UYo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely UYo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely UYo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 6 inputs namely Ri(y,2q+3), Ri(y,2q+4), RYi(y,2q+3), Ui(y,2q+3), Ui(y,2q+4), and UYi(y,2q+3); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “2q+1”) also consists of six 2:1 Muxes namely R(y,2q+4), F(y,2q+3), F(y,2q+4), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The stage (ring “y”, stage “2q+1”) also consists of two 3:1 Mux namely RY(y,2q+3) and UY(y,2q+3). The 3:1 Mux RY(y,2q+3) has three inputs namely Ri(y,2q+3), RYi(y,2q+3), and Bo(y,2q+3) and has one output RYo(y,2q+3). The 2:1 Mux R(y,2q+4) has two inputs namely Ri(y,2q+4) and Bo(y,2q+4) and has one output Ro(y,2q+4). The 2:1 Mux F(y,2q+3) has two inputs namely RYo(y,2q+3) and Ro(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely RYo(y,2q+3) and Ro(y,2q+4) and has one output Fo(y,2q+4).

The 3:1 Mux UY(y,2q+3) has three inputs namely Ui(y,2q+3), UYi(y,2q+3), and Fo(y,2q+3), and has one output UYo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely UYo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely UYo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Ri(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to two inputs namely input Ri(y,2q+4) of the stage (ring “y”, stage “q+1”) and input UYi(y,2q+1) of the stage (ring “y”, stage “q”). The output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to two inputs namely input Ui(y,2q+2) of the stage (ring “y”, stage “q”) and input RYi(y,2q+3) of the stage (ring “y”, stage “q+1”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to two inputs namely input Ri(x,2p+4) of the stage (ring “x”, stage “p+1”) and input YUi(x,2p+1) of the stage (ring “x”, stage “p”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to two inputs namely input Ui(x,2p+2) of the stage (ring “x”, stage “p”) and input YRi(x,2p+3) of the stage (ring “x”, stage “p+1”).

Referring to diagram 1400 in FIG. 14, illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 5 inputs namely Fi(x,2p+1), Fi(x,2p+2), YUi(x,2p+1), Ui(x,2p+1), and Ui(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p”) also consists of seven 2:1 Muxes namely F(x,2p+1), F(x,2p+2), YF(x,2p+1), U(x,2p+1), U(x,2p+2), B(x,2p+1), and B(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Fi(x,2p+1) and Fi(x,2p+2) and has one output Fo(x,2p+2).

The 2:1 Mux YU(x,2p+1) has two inputs namely Ui(x,2p+1) and YUi(x,2p+1) and has one output YUo(x,2p+1). The 2:1 Mux U(x,2p+1) has two inputs namely YUo(x,2p+1) and Fo(x,2p+1) and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 2:1 Mux B(x,2p+2) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 5 inputs namely Fi(x,2p+3), Fi(x,2p+4), YFi(x,2p+3), Ui(x,2p+3), and Ui(x,2p+4); and 4 outputs Bo(x,2p+3), Bo(x,2p+4), Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of seven 2:1 Muxes namely YF(x,2p+3), F(x,2p+3), F(x,2p+4), U(x,2p+3), U(x,2p+4), B(x,2p+3), and B(x,2p+4). The 2:1 Mux YF(x,2p+3) has two inputs namely Fi(x,2p+3) and YFi(x,2p+3) and has one output YFo(x,2p+3). The 2:1 Mux F(x,2p+3) has two inputs namely YFo(x,2p+3) and Fi(x,2p+4) and has one output Fo(x,2p+3). The 2:1 Mux F(x,2p+4) has two inputs namely YFo(x,2p+3) and Fi(x,2p+4) and has one output Fo(x,2p+4).

The 2:1 Mux U(x,2p+3) has two inputs namely Ui(x,2p+3) and Fo(x,2p+3) and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Ui(x,2p+4) and Fo(x,2p+4) and has one output Uo(x,2p+4). The 2:1 Mux B(x,2p+3) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Fi(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Bo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 5 inputs namely Fi(y,2q+1), Fi(y,2q+2), UYi(y,2q+1), Ui(y,2q+1), and Ui(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q”) also consists of five 2:1 Muxes namely F(y,2q+1), F(y,2q+2), U(y,2q+2), B(y,2q+1), and B(y,2q+2). The stage (ring “y”, stage “q”) also consists of one 3:1 Mux namely UY(y,2q+1). The 2:1 Mux F(y,2q+1) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+1). The 2:1 Mux F(y,2q+2) has two inputs namely Fi(y,2q+1) and Fi(y,2q+2) and has one output Fo(y,2q+2).

The 3:1 Mux UY(y,2q+1) has three inputs namely Ui(y,2q+1), UYi(y,2q+1) and Fo(y,2q+1) and has one output UYo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and Fo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely UYo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 2:1 Mux B(y,2q+2) has two inputs namely UYo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 5 inputs namely Fi(y,2q+3), Fi(y,2q+4), YFi(y,2q+3), Ui(y,2q+3), and Ui(y,2q+4); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of seven 2:1 Muxes namely YF(y,2q+3), F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux YF(y,2q+3) has two inputs namely Fi(y,2q+3) and YFi(y,2q+3) and has one output YFo(y,2q+3). The 2:1 Mux F(y,2q+3) has two inputs namely YFo(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely YFo(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and Fo(y,2q+3) and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Fi(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to two inputs namely input Fi(y,2q+4) of the stage (ring “y”, stage “q+1”) and input UYi(y,2q+1) of the stage (ring “y”, stage “q”). The output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to two inputs namely input Ui(y,2q+2) of the stage (ring “y”, stage “q”) and input YFi(y,2q+3) of the stage (ring “y”, stage “q+1”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to two inputs namely input Fi(x,2p+4) of the stage (ring “x”, stage “p+1”) and input YUi(x,2p+1) of the stage (ring “x”, stage “p”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to two inputs namely input Ui(x,2p+2) of the stage (ring “x”, stage “p”) and input YFi(x,2p+3) of the stage (ring “x”, stage “p+1”).

Referring to diagram 1500 in FIG. 15, illustrates all the connections between two arbitrary successive stages of a ring namely the stages (ring “x”, stage “p”) and (ring “x”, stage “p+1”) and two other arbitrary successive stages of any other ring namely the stages (ring “y”, stage “q”) and (ring “y”, stage “q+1”), of the complete multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s).

The stage (ring “x”, stage “p”) consists of 5 inputs namely Ri(x,2p+1), Ri(x,2p+2), Ui(x,2p+1), Ui(x,2p+2), and BYi(x,2p+2); and 4 outputs Bo(x,2p+1), Bo(x,2p+2), Fo(x,2p+1), and Fo(x,2p+2). The stage (ring “x”, stage “p”) also consists of seven 2:1 Muxes namely R(x,2p+1), R(x,2p+2), F(x,2p+1), F(x,2p+2), U(x,2p+1), U(x,2p+2), and B(x,2p+1). The stage (ring “x”, stage “p”) also consists of one 3:1 Mux namely BY(x,2p+2). The 2:1 Mux R(x,2p+1) has two inputs namely Ri(x,2p+1) and Bo(x,2p+1) and has one output Ro(x,2p+1). The 2:1 Mux R(x,2p+2) has two inputs namely Ri(x,2p+2) and Bo(x,2p+2) and has one output Ro(x,2p+2). The 2:1 Mux F(x,2p+1) has two inputs namely Ro(x,2p+1) and Ro(x,2p+2) and has one output Fo(x,2p+1). The 2:1 Mux F(x,2p+2) has two inputs namely Ro(x,2p+1), and Ro(x,2p+2), and has one output Fo(x,2p+2).

The 2:1 Mux U(x,2p+1) has two inputs namely Ui(x,2p+1) and Fo(x,2p+1) and has one output Uo(x,2p+1). The 2:1 Mux U(x,2p+2) has two inputs namely Ui(x,2p+2) and Fo(x,2p+2) and has one output Uo(x,2p+2). The 2:1 Mux B(x,2p+1) has two inputs namely Uo(x,2p+1) and Uo(x,2p+2) and has one output Bo(x,2p+1). The 3:1 Mux BY(x,2p+2) has three inputs namely Uo(x,2p+1), Uo(x,2p+2), and BYi(x,2p+2), and has one output BYo(x,2p+2).

The stage (ring “x”, stage “p+1”) consists of 5 inputs namely Ri(x,2p+3), Ri(x,2p+4), FYi(x,2p+4), Ui(x,2p+3), and Ui(x,2p+4); and 4 outputs Bo(x,2p+3), Bo(x,2p+4), Fo(x,2p+3), and Fo(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of seven 2:1 Muxes namely R(x,2p+3), R(x,2p+4), F(x,2p+3), U(x,2p+3), U(x,2p+4), B(x,2p+3), and B(x,2p+4). The stage (ring “x”, stage “p+1”) also consists of one 3:1 Mux namely FY(x,2p+4). The 2:1 Mux R(x,2p+3) has two inputs namely Ri(x,2p+3) and Bo(x,2p+3) and has one output Ro(x,2p+3). The 2:1 Mux R(x,2p+4) has two inputs namely Ri(x,2p+4) and Bo(x,2p+4) and has one output Ro(x,2p+4). The 2:1 Mux F(x,2p+3) has two inputs namely Ro(x,2p+3) and Ro(x,2p+4) and has one output Fo(x,2p+3). The 3:1 Mux FY(x,2p+4) has three inputs namely Ro(x,2p+3), Ro(x,2p+4), and FYi(x,2p+4), and has one output FYo(x,2p+4).

The 2:1 Mux U(x,2p+3) has two inputs namely Ui(x,2p+3) and Fo(x,2p+3) and has one output Uo(x,2p+3). The 2:1 Mux U(x,2p+4) has two inputs namely Ui(x,2p+4) and FYo(x,2p+4) and has one output Uo(x,2p+4). The 2:1 Mux B(x,2p+3) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+3). The 2:1 Mux B(x,2p+4) has two inputs namely Uo(x,2p+3) and Uo(x,2p+4) and has one output Bo(x,2p+4).

The output Fo(x,2p+1) of the stage (ring “x”, stage “p”) is connected to the input Ri(x,2p+3) of the stage (ring “x”, stage “p+1”). And the output Bo(x,2p+3) of the stage (ring “x”, stage “p+1”) is connected to the input Ui(x,2p+1) of the stage (ring “x”, stage “p”).

The stage (ring “y”, stage “q”) consists of 6 inputs namely Ri(y,2q+1), Ri(y,2q+2), FYi(y,2q+2), Ui(y,2q+1), Ui(y,2q+2), and BYi(y,2q+2); and 4 outputs Bo(y,2q+1), Bo(y,2q+2), Fo(y,2q+1), and Fo(y,2q+2). The stage (ring “y”, stage “q”) also consists of six 2:1 Muxes namely R(y,2q+1), R(y,2q+2), F(y,2q+1), U(y,2q+1), U(y,2q+2), and B(y,2q+1). The stage (ring “y”, stage “q”) also consists of two 3:1 Muxes namely FY(y,2q+2) and BY(y,2q+2). The 2:1 Mux R(y,2q+1) has two inputs namely Ri(y,2q+1) and Bo(y,2q+1) and has one output Ro(y,2q+1). The 2:1 Mux R(y,2q+2) has two inputs namely Ri(y,2q+2) and Bo(y,2q+2) and has one output Ro(y,2q+2). The 2:1 Mux F(y,2q+1) has two inputs namely Ro(y,2q+1) and Ro(y,2q+2) and has one output Fo(y,2q+1). The 3:1 Mux FY(y,2q+2) has three inputs namely Ro(y,2q+1), Ro(y,2q+2), and FYi(y,2q+2), and has one output FYo(y,2q+2).

The 2:1 Mux U(y,2q+1) has two inputs namely Ui(y,2q+1) and Fo(y,2q+1) and has one output Uo(y,2q+1). The 2:1 Mux U(y,2q+2) has two inputs namely Ui(y,2q+2) and FYo(y,2q+2) and has one output Uo(y,2q+2). The 2:1 Mux B(y,2q+1) has two inputs namely Uo(y,2q+1) and Uo(y,2q+2) and has one output Bo(y,2q+1). The 3:1 Mux BY(y,2q+2) has three inputs namely Uo(y,2q+1), Uo(y,2q+2), and BYi(y,2q+2) and has one output BYo(y,2q+2).

The stage (ring “y”, stage “q+1”) consists of 5 inputs namely Fi(y,2q+3), Fi(y,2q+4), YFi(y,2q+3), Ui(y,2q+3), and Ui(y,2q+4); and 4 outputs Bo(y,2q+3), Bo(y,2q+4), Fo(y,2q+3), and Fo(y,2q+4). The stage (ring “y”, stage “q+1”) also consists of seven 2:1 Muxes namely YF(y,2q+3), F(y,2q+3), F(y,2q+4), U(y,2q+3), U(y,2q+4), B(y,2q+3), and B(y,2q+4). The 2:1 Mux YF(y,2q+3) has two inputs namely Fi(y,2q+3) and YFi(y,2q+3) and has one output YFo(y,2q+3). The 2:1 Mux F(y,2q+3) has two inputs namely YFo(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+3). The 2:1 Mux F(y,2q+4) has two inputs namely YFo(y,2q+3) and Fi(y,2q+4) and has one output Fo(y,2q+4).

The 2:1 Mux U(y,2q+3) has two inputs namely Ui(y,2q+3) and Fo(y,2q+3) and has one output Uo(y,2q+3). The 2:1 Mux U(y,2q+4) has two inputs namely Ui(y,2q+4) and Fo(y,2q+4) and has one output Uo(y,2q+4). The 2:1 Mux B(y,2q+3) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+3). The 2:1 Mux B(y,2q+4) has two inputs namely Uo(y,2q+3) and Uo(y,2q+4) and has one output Bo(y,2q+4).

The output Fo(y,2q+1) of the stage (ring “y”, stage “q”) is connected to the input Fi(y,2q+3) of the stage (ring “y”, stage “q+1”). And the output Bo(y,2q+3) of the stage (ring “y”, stage “q+1”) is connected to the input Ui(y,2q+1) of the stage (ring “y”, stage “q”).

The output Fo(x,2p+2) of the stage (ring “x”, stage “p”) is connected via the wire Hop(1,1) to two inputs namely input Fi(y,2q+4) of the stage (ring “y”, stage “q+1”) and input BYi(y,2q+1) of the stage (ring “y”, stage “q”). The output Bo(x,2p+4) of the stage (ring “x”, stage “p+1”) is connected via the wire Hop(1,2) to two inputs namely input Ui(y,2q+2) of the stage (ring “y”, stage “q”) and input YFi(y,2q+3) of the stage (ring “y”, stage “q+1”).

The output Fo(y,2q+2) of the stage (ring “y”, stage “q”) is connected via the wire Hop(2,1) to two inputs namely input Ri(x,2p+4) of the stage (ring “x”, stage “p+1”) and input BYi(x,2p+1) of the stage (ring “x”, stage “p”). The output Bo(y,2q+4) of the stage (ring “y”, stage “q+1”) is connected via the wire Hop(2,2) to two inputs namely input Ui(x,2p+2) of the stage (ring “x”, stage “p”) and input YFi(x,2p+4) of the stage (ring “x”, stage “p+1”).

In accordance with the current invention, either partial multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s) 100A of FIG. 1A, or partial multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s) 100B of FIG. 1B, or partial multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s) 100C of FIG. 1C, or one or more slices of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D of FIG. 1D, corresponding to a block of 2D-grid of blocks 800 of FIG. 8, using any one of the embodiments of 200A-200F of FIGS. 2A-2F, 900A-900E of FIGS. 9A-9E, 1000A-1000F of FIGS. 10A-10F, 1100A-1100C of FIGS. 11A-11C to implement a stage of a ring of the multi-stage pyramid network, either by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks described in diagram 700A of FIG. 7A may be any one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B is very efficient in the reduction of the die size, power consumption, and highly optimized for lower wire/path delay for higher performance for practical routing applications to particularly to set up broadcast, unicast and multicast connections. Also all embodiments disclosed in the current invention may be implemented only partially i.e. a mux or a wire may not implemented to save area, number of wires, power or for any reason. In general in accordance with the current invention, where N₁ and N₂ of the complete multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s) may be arbitrarily large in size and also the 2D-grid size 800 may also be arbitrarily large in size in terms of both the number of rows and number of columns.

1) Programmable Integrated Circuit Embodiments

All the embodiments disclosed in the current invention are useful in programmable integrated circuit applications. FIG. 16A2 illustrates the detailed diagram 1600A2 for the implementation of the diagram 1600A1 in programmable integrated circuit embodiments. Each crosspoint is implemented by a transistor coupled between the corresponding inlet link and outlet link, and a programmable cell in programmable integrated circuit embodiments. Specifically crosspoint CP(1,1) is implemented by transistor C(1,1) coupled between inlet link IL1 and outlet link OL1, and programmable cell P(1,1); crosspoint CP(1,2) is implemented by transistor C(1,2) coupled between inlet link IL1 and outlet link OL2, and programmable cell P(1,2); crosspoint CP(2,1) is implemented by transistor C(2,1) coupled between inlet link IL2 and outlet link OL1, and programmable cell P(2,1); and crosspoint CP(2,2) is implemented by transistor C(2,2) coupled between inlet link IL2 and outlet link OL2, and programmable cell P(2,2).

If the programmable cell is programmed ON, the corresponding transistor couples the corresponding inlet link and outlet link. If the programmable cell is programmed OFF, the corresponding inlet link and outlet link are not connected. For example if the programmable cell P(1,1) is programmed ON, the corresponding transistor C(1,1) couples the corresponding inlet link IL1 and outlet link OL1. If the programmable cell P(1,1) is programmed OFF, the corresponding inlet link IL1 and outlet link OL1 are not connected. In volatile programmable integrated circuit embodiments the programmable cell may be an SRAM (Static Random Address Memory) cell. In non-volatile programmable integrated circuit embodiments the programmable cell may be a Flash memory cell. Also the programmable integrated circuit embodiments may implement field programmable logic arrays (FPGA) devices, or programmable Logic devices (PLD), or Application Specific Integrated Circuits (ASIC) embedded with programmable logic circuits or 3D-FPGAs.

FIG. 16A2 also illustrates a buffer B1 on inlet link IL2. The signals driven along inlet link IL2 are amplified by buffer Bl. Buffer B1 can be inverting or non-inverting buffer. Buffers such as B1 are used to amplify the signal in links which are usually long.

In other embodiments all the d*d switches described in the current invention are also implemented using muxes of different sizes controlled by SRAM cells or flash cells etc.

2) One-Time Programmable Integrated Circuit Embodiments

All the embodiments disclosed in the current invention are useful in one-time programmable integrated circuit applications. FIG. 16A3 illustrates the detailed diagram 1600A3 for the implementation of the diagram 1600A1 in one-time programmable integrated circuit embodiments. Each crosspoint is implemented by a via coupled between the corresponding inlet link and outlet link in one-time programmable integrated circuit embodiments. Specifically crosspoint CP(1,1) is implemented by via V(1,1) coupled between inlet link IL1 and outlet link OL1; crosspoint CP(1,2) is implemented by via V(1,2) coupled between inlet link IL1 and outlet link OL2; crosspoint CP(2,1) is implemented by via V(2,1) coupled between inlet link IL2 and outlet link OL1; and crosspoint CP(2,2) is implemented by via V(2,2) coupled between inlet link IL2 and outlet link OL2.

If the via is programmed ON, the corresponding inlet link and outlet link are permanently connected which is denoted by thick circle at the intersection of inlet link and outlet link. If the via is programmed OFF, the corresponding inlet link and outlet link are not connected which is denoted by the absence of thick circle at the intersection of inlet link and outlet link. For example in the diagram 1600A3 the via V(1,1) is programmed ON, and the corresponding inlet link IL1 and outlet link OL1 are connected as denoted by thick circle at the intersection of inlet link IL1 and outlet link OL1; the via V(2,2) is programmed ON, and the corresponding inlet link IL2 and outlet link OL2 are connected as denoted by thick circle at the intersection of inlet link IL2 and outlet link OL2; the via V(1,2) is programmed OFF, and the corresponding inlet link IL1 and outlet link OL2 are not connected as denoted by the absence of thick circle at the intersection of inlet link IL1 and outlet link OL2; the via V(2,1) is programmed OFF, and the corresponding inlet link IL2 and outlet link OL1 are not connected as denoted by the absence of thick circle at the intersection of inlet link IL2 and outlet link OL1. One-time programmable integrated circuit embodiments may be anti-fuse based programmable integrated circuit devices or mask programmable structured ASIC devices.

3) Integrated Circuit Placement and Route Embodiments

All the embodiments disclosed in the current invention are useful in Integrated Circuit Placement and Route applications, for example in ASIC backend Placement and Route tools. FIG. 16A4 illustrates the detailed diagram 1600A4 for the implementation of the diagram 1600A1 in Integrated Circuit Placement and Route embodiments. In an integrated circuit since the connections are known a-priori, the switch and crosspoints are actually virtual. However the concept of virtual switch and virtual crosspoint using the embodiments disclosed in the current invention reduces the number of required wires, wire length needed to connect the inputs and outputs of different netlists and the time required by the tool for placement and route of netlists in the integrated circuit.

Each virtual crosspoint is used to either to hardwire or provide no connectivity between the corresponding inlet link and outlet link. Specifically crosspoint CP(1,1) is implemented by direct connect point DCP(1,1) to hardwire (i.e., to permanently connect) inlet link IL1 and outlet link OL1 which is denoted by the thick circle at the intersection of inlet link IL1 and outlet link OL1; crosspoint CP(2,2) is implemented by direct connect point DCP(2,2) to hardwire inlet link IL2 and outlet link OL2 which is denoted by the thick circle at the intersection of inlet link IL2 and outlet link OL2. The diagram 1600A4 does not show direct connect point DCP(1,2) and direct connect point DCP(1,3) since they are not needed and in the hardware implementation they are eliminated. Alternatively inlet link IL1 needs to be connected to outlet link OL1 and inlet link IL1 does not need to be connected to outlet link OL2. Also inlet link IL2 needs to be connected to outlet link OL2 and inlet link IL2 does not need to be connected to outlet link OL1. Furthermore in the example of the diagram 1600A4, there is no need to drive the signal of inlet link IL1 horizontally beyond outlet link OL1 and hence the inlet link IL1 is not even extended horizontally until the outlet link OL2. Also the absence of direct connect point DCP(2,1) illustrates there is no need to connect inlet link IL2 and outlet link OL1.

In summary in integrated circuit placement and route tools, the concept of virtual switches and virtual cross points is used during the implementation of the placement & routing algorithmically in software, however during the hardware implementation cross points in the cross state are implemented as hardwired connections between the corresponding inlet link and outlet link, and in the bar state are implemented as no connection between inlet link and outlet link.

3) More Application Embodiments

All the embodiments disclosed in the current invention are also useful in the design of SoC interconnects, Field programmable interconnect chips, parallel computer systems and in time-space-time switches.

Scheduling Method Embodiments the Multi-Stage Pyramid Network V_(Comb)(N₁,N₂,d,s):

FIG. 17 shows a high-level flowchart of a scheduling method 1700, in one embodiment executed to setup multicast and unicast connections in the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) disclosed in this invention. According to this embodiment, the set of multicast connections are initialized to the beginning of the set in act 1710. Then the control goes to act 1720. In act 1720, next multicast connection is selected in sequence form the set of multicast connections. Then the control goes to act 1730.

In act 1730 it is checked if this is the next multicast connection in sequence is NULL or i.e. all the multicast connections are scheduled. If act 1730 results “no”, that is there are more multicast connections to be scheduled the control goes to act 1740. In act 1740 it is checked if this multicast connection is being scheduled for the first time. Or if it is not scheduled for the first time, it is checked if any one of the links taken by this multicast connection is oversubscribed by any other multicast connection is checked. If either the multicast connection is being scheduled for the first time or if any one of the links taken by this multicast connection is oversubscribed the control goes to act 1750. Otherwise control goes to act 1720 where the next multicast connection will be selected. So act 1720, act 1730, and act 1740 are executed iteratively in a loop.

In act 1750 the multicast connection is not being scheduled for the first time and since at least one of the links taken by this multicast connection is oversubscribed, the complete path taken this multicast connection is cleared or the multicast connection's path is ripped. Then the control goes to act 1760. In act 1760, using the well-known A* search algorithm the least cost path from its source outlet link of the computational block to all the target inlet links of the corresponding computational blocks are found out one after another target inlet links. The cost function used is based on the Manhattan distance between the target inlet link's block and source outlet link's block by taking the delays on each wire is considered in the cost function and also that longest wires are chosen first in the A* search algorithm.

According to the current invention, before scheduling the set of multicast connections in the scheduling method 1700, first a set of static cost tables will be prepared with the least cost paths from each link of the partial multistage network V_(Comb)(N₁,N₂,d,s) to each outgoing hop wire from that partial multistage network as well as to each inlet link of the computational block connected form that partial multistage network. So there will be as many cost tables created equal to the sum of the total number of outgoing hop wires from the partial multistage network and the inlet links of the computational block connected form that partial multistage network. Each cost table will also have as many entries as there are internal links of that partial multistage network. And the value at each entry of these cost tables is equal to the total delay from the corresponding internal link to the corresponding outgoing hop wire or to the inlet link of the computational block.

In act 1760, according to the current invention, for the look-ahead cost computation during the A* search algorithm both the cost from the static cost tables from the current internal link in the current partial multistage network and the cost value computed based on the Manhattan distance between the target inlet link's block and the current link's corresponding block by taking the delays on each wire into consideration are added. Also the least of the cost values from all the cost tables corresponding to the current link and all the outgoing wires in the right direction of the target block, is selected before it is added to the Manhattan distance based cost. Finally in act 1760, the multicast connection is scheduled as for the A* search algorithm. Then the control goes to act 1770.

In act 1770, the demand cost and history cost of each link used by the current multicast connection are updated. And the control goes to act 1720. Thus act 1720, act 1730, act 1740, act 1750, act 1760, and act 1770 are executed in a loop to schedule the multicast connections by going through the list of all multicast connections which will be one pass or iteration.

In act 1730 results “yes”, i.e. all the required multicast connections in the list are scheduled in this pass or iteration, then the control goes to act 1780. In act 1780, the total number of links in the complete multistage network that are taken by more than one multicast connection are counted, hereinafter “OSN” or “Over Subscription nodes”. Then the control goes to act 1790. In act 1790 it will be checked and if OSN is not equal to zero then the act 1790 results in “no” and the control goes to act 1710 to start the next iteration or pass to schedule all the required multicast connections in the list of all multicast connections. Thus act 1710, act 1720, act 1730, act 1740, act 1750, act 1760, act 1770, act 1780, and act 1790 are executed in a loop to implement different passes or iterations of scheduling the set of all multicast connections. If the act 1790 results in “yes”, that means no link in the complete multistage network is taken by more than one multicast connection and hence the scheduling is successfully completed.

Each multicast connection of the type described above in reference to method 1700 of FIG. 17 can be unicast connection, a multicast connection or a broadcast connection, depending on the example.

Inter-Block and Intra-Block Scheduling Method Embodiments the Multi-Stage Pyramid Network V_(Comb)(N₁,N₂,d,s):

FIG. 18 shows a high-level flowchart of a scheduling method 1800, in one embodiment executed to setup multicast connections in the multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) disclosed in this invention in two steps (one for each act 1810 and act 1820 as shown in FIG. 18) namely: 1) scheduling the set of multicast connections outside the blocks of 2D-grid of blocks with each block corresponding to a partial multi-stage network, or in between the blocks of the complete multi-stage network, or alternatively on the external wires of the complete multi-stage network hereinafter “inter-block scheduling”. Inter-block scheduling is implemented in act 1810 so that there are no OSN nodes. During inter-block scheduling the partial multi-stage pyramid network corresponding to each block is considered as a single stage network or alternatively each internal wire of the partial multi-stage pyramid network is directly connected to each outgoing wire or external wire of the partial multi-stage pyramid network, and 2) scheduling the set of multicast connections inside the blocks of 2D-grid of blocks with each block corresponding to a partial multi-stage network or alternatively on the internal wires of the complete multi-stage network hereinafter “intra-block scheduling”. The act 1820 implements intra-block scheduling for each block so that there are no OSN nodes.

The act 1810 may be implemented by the scheduling method 1700 of FIG. 17. Similarly in act 1820 for each block of the multi-stage pyramid network, the inter-block scheduling may be implemented by the scheduling method 1700 of FIG. 17.

In accordance with the current invention, the scheduling method 1700 of FIG. 17 and the scheduling method 1800 of FIG. 18 are applicable to either partial multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s) 100A of FIG. 1A, or partial multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s) 100B of FIG. 1B, or partial multi-stage pyramid network V_(D-Comb)(N₁,N₂,d,s) 100C of FIG. 1C, or one or more slices of partial multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) 100D of FIG. 1D, corresponding to a block of 2D-grid of blocks 800 of FIG. 8, using any one of the embodiments of 200A-200F of FIGS. 2A-2F, 900A-900E of FIGS. 9A-9E, 1000A-1000F of FIGS. 10A-10F, 1100A-1100C of FIGS. 11A-11C to implement a stage of a ring of the multi-stage pyramid network, either by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks described in diagram 700A of FIG. 7A may be any one of the embodiments of either the diagrams 300A of FIG. 3A, 300B of FIG. 3B, 300C of FIG. 3C, 300D of FIG. 3D, 300E of FIG. 3E, 500A of FIG. 5A, 1200 of FIG. 12, 1300 of FIG. 13, 1400 of FIG. 14, and 1500 of FIG. 15 or by using the hop wire connections or multi-drop hop wire connections between two arbitrary stages in two different rings of the same block or two different rings of different blocks may be any one of the embodiments of either the diagrams 400A of FIG. 4A, 400B of FIG. 4B, 400C of FIG. 4C, 400D of FIG. 4D, 600A of FIG. 6A, or 600B of FIG. 6B is very efficient in the reduction of the die size, power consumption, and highly optimized for lower wire/path delay for higher performance for practical routing applications to particularly to set up broadcast, unicast and multicast connections.

Method and System for Automatic Multi-Stage Pyramid Network V_(Comb)(N₁,N₂,d,s) Based Fabric Generation for Including FPGA's:

Generation of optimal multi-stage pyramid network based fabric for an integrated device, for example an FPGA device, with 2D-grid of computational blocks with their given number of inlet links and outlet links, and for the given set of benchmarks or hardware designs so that all the benchmarks are routed by the generated multi-stage pyramid network V_(Comb)(N₁,N₂,d,s) based fabric ultimately to emulate all the benchmarks is disclosed in the current invention. Numerous diagrams are disclosed with different variations of embodiments in the current invention. However each particular embodiment has its own benefits over other embodiments as each of them optimize a particular set of goals.

FIG. 19 shows a high-level flowchart of a method 1900, in one embodiment executed in a programmed processor to generate optimal multi-stage pyramid network based fabric for an integrated device including FPGA's. In acts 1910, 1920, and 1930 using the embodiments disclosed in the current invention a partial multi-stage pyramid network or subnetwork is chosen for each computational block or sub-integrated circuit.

In act 1910, number of inlet links and outlet links to each computational block which may be a LUT or a cluster of LUTs, memory, DSP processing block are counted. Each computing block may or may not have the same number of inlet links and outlet links. If they are not the same then act 1910 gets the number of inlet links as the maximum inlet links of all the computing blocks, and sets it as “In”. Then it sets the initial number of rings, r is equal to “In” divided by 4 and sets the number of stages for all the rings, is equal to “In” divided by 2. Then the number of slices “Sl” is selected as given by the user or read from a configuration file. Then the control goes to act 1920.

In act 1920, the number of External Hop Wires of given hop length and the number of external hop wires with zero or more multi-drop hop wires in each of the four directions (two horizontal and two vertical directions) again given by the user or read from a configuration file are selected. Then the total number of stages needed is incremented by total number of external hop wires divided by 2. Then the number of stages for each slice “SSl” is computed by dividing the total number of stages by number of slices. Then the number of stages per ring is computed by dividing “SSl” by “r”. Next act 1920 increments the number of stages so that each ring has at least one stage to connect exclusively to every other ring in its slice. Then number and size of multiplexers in each stage are selected as given by the user or read from a configuration file. Finally act 1920 chooses the type of connections between stages of rings as either between same numbered stages (same level) or different level switches if needed using the hop wire connection chart 700A in FIG. 7A. Then the control goes to 1930.

In act 1930, the connections between stages or muxes are fine-tuned manually as needed and thus the partial multi-stage pyramid network is finalized for each computational block. In another embodiment act 1930 may be automatic or programmed act by the programmed processor without manual intervention. Then the control goes to act 1940. In act 1940 the software tool automatically simulates the complete integrated device with the required number of rows and columns of sub-integrated circuit blocks or computational blocks along with the partial multi-stage pyramid network finalized in act 1930. Then in act 1950, first the benchmarks to be routed in the integrated device are selected and then each of them is routed using one of the scheduling methods of 1700 of FIG. 17 or 1800 of FIG. 18.

Then in act 1960, it is checked if all the benchmarks are successfully routed. If it results in “NO” then the control goes to act 1970. In act 1970, one or more of the parameters described in acts in 1910 or 1920 are changed and the control transfers to act 1930. Thus the acts 1930, 1940, 1950, 1960 and 1970 are executed in a loop iteratively until the act 1960 results in “YES”. Then the control goes to act 1980. Now for the selected multi-stage pyramid network area, power, performance and routing run-time speed numbers are computed. Then the control goes to act 1990 where it is checked if all the goals are met as per a desired specific criteria. If act 1990 results in “NO”, then the control goes to act 1995. In act 1995, one or more parameters of the partial multi-stage pyramid network are optimized and then the control goes to act 1930. So acts 1930, 1940, 1950, 1960, 1980, 1990, and 1995 are executed in a loop iteratively until act 1990 results in “YES”. Then the control moves to act 1999. In act 1999 the final and optimized multi-stage pyramid network is saved and the method 1900 exits.

Numerous modifications and adaptations of the embodiments, implementations, and examples described herein will be apparent to the skilled artisan in view of the disclosure. 

What is claimed is:
 1. A system for generating a multi-stage pyramid network, said multi-stage pyramid network including connections to a plurality of computational blocks of a semiconductor integrated circuit arranged in a two-dimensional grid of a plurality of rows and a plurality of columns, said plurality of computational blocks comprising a plurality of inlet links and a plurality of outlet links; and wherein said multi-stage pyramid network comprising a plurality of partial multi-stage pyramid networks wherein each computational block of said plurality of computational blocks coupled to at least one of said plurality of partial multi-stage pyramid networks via said plurality of inlet links and said plurality of outlet links; and each partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks comprising one or more slices, each slice of said one or more slices comprising one or more rings, each ring of said one or more rings comprising a plurality of stages; and each stage of said plurality of stages comprising one or more switches of size d_(i)×d₀, where d_(i), d₀ are integers, d_(i)≥2 and d₀≥2, each switch of said one or more switches of size d_(i)×d₀ having d_(i) incoming links and d₀ outgoing links, each switch of said one or more switches of size d_(i)×d₀ comprising a plurality of multiplexers of size d≥2, where d is an integer, with each multiplexer of said plurality of multiplexers comprising d inputs and one output; and wherein said at least one switch of size d_(i)×d₀ comprises one of a) a forward switch, b) both a forward switch and a U-turn switch, c) a forward switch, a backward switch and a U-turn switch, d) a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch e) a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree turn paths, f) an integrated switch of a forward switch, a backward switch and U-turn switch, g) an integrated switch of a forward switch, a backward switch and a U-turn switch without 180 degree turn paths h) an integrated switch of a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch and i) an integrated switch comprising a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree turn paths; and wherein said d_(i) incoming links and said d₀ outgoing links comprise one or more internal connections and one or more hop wires; and wherein each inlet link of said plurality of inlet links is connected to the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings of a first slice of said one or more slices of a first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks, and each outlet link of said plurality of outlet links is connected to a first input of said d inputs of one or more multiplexers of said plurality of multiplexers of one or more switches of said one or more switches of one or more stages of said plurality of stages of one or more rings of said one or more rings of one or more slices of said one or more slices of one or more partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks; and wherein a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said plurality of inlet links as a second partial multi-stage network of said plurality of partial multi-stage networks; and a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said plurality of outlet links as a second partial multi-stage network of said plurality of partial multi-stage networks; a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said one or more slices as a second partial multi-stage network of said plurality of partial multi-stage networks; a first slice of said one or more slices comprises one of a) a same number and b) a different number of said one or more rings as a second slice of said one or more slices; a first ring of said one or more rings comprises one of a) a same number and b) a different number of said plurality of stages as a second ring of said one or more rings; and a first stage of said plurality of stages comprises one of a) a same number and b) a different number of said one or more switches of size d_(i)×d₀ as a second stage of said plurality of stages; a first switch of said one or more switches of size d_(i)×d₀ is one of a) a same size and b) a different size as a second switch of said one or more switches of size d_(i)×d₀; and a first multiplexer in said plurality of multiplexers of size d≥2 is one of a) a same size and b) a different size as a second multiplexer in said plurality of multiplexers of size d≥2; and wherein each internal connection of said one or more internal connections connected from the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings to one of the d inputs of a second multiplexer of said plurality of multiplexers of a second switch of said one or more switches of a second stage of said plurality of stages of said first ring of said one or more rings; and wherein said one or more hop wires comprise one or more internal hop wires and one or more external hop wires; and wherein each internal hop wire of said one or more internal hop wires connected from the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings of a first slice of said one or more slices of a first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks to one or more of the d inputs of one or more different multiplexers from said first multiplexer of said plurality of multiplexers of one or more different switches from said first switch of said one or more switches of one or more different stages from said first stage of said plurality of stages of one or more different rings from said first ring of said one or more rings of said first slice of said one or more slices of said first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; and wherein each external hop wire of said one or more external hop wires connected from the output of a multiplexer of said plurality of multiplexers of a switch of said one or more switches of a stage of said plurality of stages of a ring of said one or more rings of a slice of said one or more slices of a first said partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks to one or more inputs of said d inputs of one or more multiplexers of said plurality of multiplexers of one or more switches of said one or more switches of said plurality of stages of one or more stages of said one or more rings of a slice of said one or more slices of one or more partial multi-stage pyramid networks different from first said partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; and wherein one or more external hop wires of said one or more of external hop wires are one of a) connected between multiplexers of said plurality of multiplexers of switches of said one or more switches of same stages of said plurality of stages in two or more different partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks and b) connected between multiplexers of said plurality of multiplexers of switches of said one or more switches of in different stages said plurality of stages in two or more different partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks, said system comprising: one or more processors; a memory arrangement coupled to said one or more processors, the memory arrangement configured with instructions that when executed by said one or more processors cause said one or more processors to perform operations including: setting up size of said one or more slices, setting up size of said one or more rings, setting up size of said plurality of stages, setting up size of said one or more switches, setting up size of said plurality of multiplexers, setting up number of inputs of each multiplexer of said plurality of multiplexers; setting up connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks; setting up connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings; selecting hop length of each external hop wire of said one or more external hop wires setting up connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks; setting up connections of said one or more internal hop wires between said one or more rings of the same slice of said one or more slices of a partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; setting up size of said plurality of rows and size of said plurality of columns in said two-dimensional grid; simulating said semiconductor integrated circuit with said plurality of rows and said plurality of columns of said plurality of partial multi-stage pyramid networks; routing one or more benchmarks on said semiconductor integrated circuit; checking if said one or more benchmarks are successfully routed; checking if all benchmarks of said one or more benchmarks are successfully routed, then computing a plurality of metrics including area, power, performance of benchmark and routing speed; checking if all benchmarks of said one or more benchmarks have met a criteria and saving said multi-stage pyramid network, or checking if said one or more benchmarks are not successfully routed, then changing either a) one or more of said size of said one or more slices, or b) said size of said one or more rings, or c) said size of said plurality of stages, or d) said size of said one or more switches, or e) said size of said plurality of multiplexers, or f) said number of inputs of each multiplexer of said plurality of multiplexers, or g) said connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks, or h) said hop length of each external hop wire of said one or more external hop wires, or i) said setting up of connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks, or j) said setting up of connections of said one or more internal hop wires between said one or more rings, or k) said setting up of connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings, or l) said size of said plurality of rows in said two-dimensional grid, or m) said size of said plurality of columns in said two-dimensional grid.
 2. The system of claim 1, wherein said operations, Said setting up size of said one or more slices, said setting up size of said one or more rings, said setting up size of said plurality of stages, said setting up size of said one or more switches, said setting up size of said plurality of multiplexers, said setting up number of inputs of each multiplexer of said plurality of multiplexers; said setting up connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks; said setting up connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings, and said selecting hop length of each external hop wire of said one or more external hop wires wherein size determines hop length, said setting up connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks; said setting up connections of said one or more internal hop wires between said one or more rings of the same slice of said one or more slices of a partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; said setting up size of said plurality of rows and size of said plurality of columns in said two-dimensional grid; said simulating said semiconductor integrated circuit with said plurality of rows and said plurality of columns of said plurality of partial multi-stage pyramid networks; said routing one or more benchmarks on said semiconductor integrated circuit; said checking if said one or more benchmarks are successfully routed; said checking if all benchmarks of said one or more benchmarks are successfully routed, then computing a plurality of metrics including area, power, performance of benchmark and routing speed; said checking if all benchmarks of said one or more benchmarks have met a criteria and saving said multi-stage pyramid network, or said checking if said one or more benchmarks are not successfully routed, then changing either a) one or more of said size of said one or more slices, or b) said size of said one or more rings, or c) said size of said plurality of stages, or d) said size of said one or more switches, or e) said size of said plurality of multiplexers, or f) said number of inputs of each multiplexer of said plurality of multiplexers, or g) said connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks, or h) said hop length of each external hop wire of said one or more external hop wires, or i) said setting up of connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks, or j) said setting up of connections of said one or more internal hop wires between said one or more rings, or k) said setting up of connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings, or l) said size of said plurality of rows in said two-dimensional grid, or m) said size of said plurality of columns in said two-dimensional grid, are repeated in a plurality of iterations, until said one or more benchmarks have met said criteria and saving said multi-stage pyramid network.
 3. The system of claim 1, wherein each partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks is replicated in either said rows or said columns of said two-dimensional grid.
 4. The system of claim 1, wherein one or more said operations are performed manually.
 5. The system of claim 2, wherein in an iteration of said plurality of iterations, either one or more multiplexers of said plurality of multiplexers are removed including connections to its said inputs and said output or one or more multiplexers are added to said plurality of multiplexers including connections to its said inputs from one or more multiplexers of said plurality of multiplexers and connection to its said output to a first multiplexer of said plurality of multiplexers.
 6. The system of claim 1, wherein in an iteration of said plurality of iterations, either one or more internal connections of said one or more internal connections are removed, or one or more internal hop wires of said one or more internal hop wires are removed, or one or more external hop wires of said one or more external hop wires are removed, or one or more internal connections are added to said one or more internal connections, or one or more internal hop wires are added to said one or more internal hop wires, or one or more external hop wires are added to said one or more external hop wires.
 7. The system of claim 1, wherein said plurality of computational blocks comprise either LUTs or memory or DSP processing block.
 8. The system of claim 1, wherein said semiconductor integrated circuit comprises a field programmable gate array.
 9. A method of generating a multi-stage pyramid network, said multi-stage pyramid network including connections to a plurality of computational blocks of a semiconductor integrated circuit arranged in a two-dimensional grid of a plurality of rows and a plurality of columns, said plurality of computational blocks comprising a plurality of inlet links and a plurality of outlet links; and wherein said multi-stage pyramid network comprising a plurality of partial multi-stage pyramid networks and each partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks coupled to at least one of said plurality of computational blocks via said plurality of inlet links and said plurality of outlet links; and each partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks comprising one or more slices, each slice of said one or more slices comprising one or more rings, each ring of said one or more rings comprising a plurality of stages; and each stage of said plurality of stages comprising one or more switches of size d_(i)×d₀, where d_(i), d_(o) are integers, d_(i)≥2 and d_(o)≥2, each switch of said one or more switches of size d_(i)×d₀ having d_(i) incoming links and d₀ outgoing links, each switch of said one or more switches of size d_(i)×d₀ comprising a plurality of multiplexers of size d≥2, where d is an integer, with each multiplexer of said plurality of multiplexers comprising d inputs and one output; and wherein said at least one switch of size d_(i)×d₀ comprises one of a) a forward switch, b) both a forward switch and a U-turn switch, c) a forward switch, a backward switch and a U-turn switch, d) a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch e) a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree turn paths, f) an integrated switch of a forward switch, a backward switch and U-turn switch, g) an integrated switch of a forward switch, a backward switch and a U-turn switch without 180 degree turn paths h) an integrated switch of a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch and i) an integrated switch comprising a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree turn paths; and wherein said d_(i) incoming links and said d_(o) outgoing links comprises one or more internal connections and one or more hop wires; and wherein each inlet link of said plurality of inlet links is connected to the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings of a first slice of said one or more slices of a first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks, and each outlet link of said plurality of outlet links is connected to a first input of said d inputs of one or more multiplexers of said plurality of multiplexers of one or more switches of said one or more switches of one or more stages of said plurality of stages of one or more rings of said one or more rings of one or more slices of said one or more slices of one or more partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks; and wherein a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said plurality of inlet links as a second partial multi-stage network of said plurality of partial multi-stage networks; and a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said plurality of outlet links as a second partial multi-stage network of said plurality of partial multi-stage networks; a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said one or more slices as a second partial multi-stage network of said plurality of partial multi-stage networks; a first slice of said one or more slices comprises one of a) a same number and b) a different number of said one or more rings as a second slice of said one or more slices; a first ring of said one or more rings comprises one of a) a same number and b) a different number of said plurality of stages as a second ring of said one or more rings; and a first stage of said plurality of stages comprises one of a) a same number and b) a different number of said one or more switches of size d_(i)×d₀ as a second stage of said plurality of stages; a first switch of said one or more switches of size d_(i)×d₀ is one of a) a same size and b) a different size as a second switch of said one or more switches of size d_(i)×d₀; and a first multiplexer in said plurality of multiplexers of size d≥2 is one of a) a same size and b) a different size as a second multiplexer in said plurality of multiplexers of size d≥2; and wherein each internal connection of said one or more internal connections connected from the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings to one of the d inputs of a second multiplexer of said plurality of multiplexers of a second switch of said one or more switches of a second stage of said plurality of stages of said first ring of said one or more rings; and wherein said hop wires comprise one or more internal hop wires and one or more external hop wires; and wherein each internal hop wire of said one or more internal hop wires connected from the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings of a first slice of said one or more slices of a first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks to one or more of the d inputs of one or more different multiplexers from said first multiplexer of said plurality of multiplexers of one or more different switches from said first switch of said one or more switches of one or more different stages from said first stage of said plurality of stages of one or more different rings from said first ring of said one or more rings of said first slice of said one or more slices of said first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; and wherein each external hop wire of said one or more external hop wires connected from the output of a multiplexer of said plurality of multiplexers of a switch of said one or more switches of a stage of said plurality of stages of a ring of said one or more rings of a slice of said one or more slices of a first said partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks to one or more inputs of said d inputs of one or more multiplexers of said plurality of multiplexers of one or more switches of said one or more switches of said plurality of stages of one or more stages of said one or more rings of a slice of said one or more slices of one or more partial multi-stage pyramid networks different from first said partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; and wherein one or more external hop wires of said one or more external hop wires are one of a) connected between multiplexers of said plurality of multiplexers of switches of said one or more switches of same stages of said plurality of stages in two or more different partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks and b) connected between multiplexers of said plurality of multiplexers of switches of said one or more switches of in different stages said plurality of stages in two or more different partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks, said method comprising: using one or more programmed processors to perform steps including: setting up size of said one or more slices, setting up size of said one or more rings, setting up size of said plurality of stages, setting up size of said one or more switches, setting up size of said plurality of multiplexers, setting up number of inputs of each multiplexer of said plurality of multiplexers; setting up connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks; setting up connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings; selecting hop length of each external hop wire of said one or more external hop wires setting up connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks; setting up connections of said one or more internal hop wires between said one or more rings of the same slice of said one or more slices of a partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; setting up size of said plurality of rows and size of said plurality of columns in said two-dimensional grid; simulating said semiconductor integrated circuit with said plurality of rows and said plurality of columns of said plurality of partial multi-stage pyramid networks; routing one or more benchmarks on said semiconductor integrated circuit; checking if said one or more benchmarks are successfully routed; checking if all benchmarks of said one or more benchmarks are successfully routed, then computing a plurality of metrics including area, power, performance of benchmark and routing speed; checking if all benchmarks of said one or more benchmarks have met a criteria and saving said multi-stage pyramid network, or checking if said one or more benchmarks are not successfully routed, then changing either a) one or more of said size of said one or more slices, or b) said size of said one or more rings, or c) said size of said plurality of stages, or d) said size of said one or more switches, or e) said size of said plurality of multiplexers, or f) said number of inputs of each multiplexer of said plurality of multiplexers, or g) said connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks, or h) said hop length of each external hop wire of said one or more external hop wires, or i) said setting up of connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks, or j) said setting up of connections of said one or more internal hop wires between said one or more rings, or k) said setting up of connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings, or l) said size of said plurality of rows in said two-dimensional grid, or m) said size of said plurality of columns in said two-dimensional grid.
 10. The method of claim 9, wherein said steps, Said setting up size of said one or more slices, said setting up size of said one or more rings, said setting up size of said plurality of stages, said setting up size of said one or more switches, said setting up size of said plurality of multiplexers, said setting up number of inputs of each multiplexer of said plurality of multiplexers; said setting up connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks; said setting up connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings; said selecting hop length of each external hop wire of said one or more external hop wires wherein size determines hop length, said setting up connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks; said setting up connections of said one or more internal hop wires between said one or more rings of the same slice of said one or more slices of a partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; said setting up size of said plurality of rows and size of said plurality of columns in said two-dimensional grid; said simulating said semiconductor integrated circuit with said plurality of rows and said plurality of columns of said plurality of partial multi-stage pyramid networks; said routing one or more benchmarks on said semiconductor integrated circuit; said checking if said one or more benchmarks are successfully routed; said checking if all benchmarks of said one or more benchmarks are successfully routed, then computing a plurality of metrics including area, power, performance of benchmark and routing speed; said checking if all benchmarks of said one or more benchmarks have met a criteria and saving said multi-stage pyramid network, or said checking if said one or more benchmarks are not successfully routed, then changing either a) one or more of said size of said one or more slices, or b) said size of said one or more rings, or c) said size of said plurality of stages, or d) said size of said one or more switches, or e) said size of said plurality of multiplexers, or f) said number of inputs of each multiplexer of said plurality of multiplexers, or g) said connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks, or h) said hop length of each external hop wire of said one or more external hop wires, or i) said setting up of connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks, or j) said setting up of connections of said one or more internal hop wires between said one or more rings, or k) said setting up of connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings, or l) said size of said plurality of rows in said two-dimensional grid, or m) said size of said plurality of columns in said two-dimensional grid, are repeated in a plurality of iterations, until said one or more benchmarks have met said criteria and saving said multi-stage pyramid network.
 11. The method of claim 9, wherein each partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks is replicated in either said rows or said columns of said two-dimensional grid.
 12. The method of claim 9, wherein one or more said steps are performed manually.
 13. The method of claim 10, wherein in an iteration of said plurality of iterations, either one or more multiplexers of said plurality of multiplexers are removed including connections to its said inputs and said output or one or more multiplexers are added to said plurality of multiplexers including connections to its said inputs from one or more multiplexers of said plurality of multiplexers and connection to its said output to a first multiplexer of said plurality of multiplexers.
 14. The method of claim 9, wherein in an iteration of said plurality of iterations, either one or more internal connections of said one or more internal connections are removed, or one or more internal hop wires of said one or more internal hop wires are removed, or one or more external hop wires of said one or more external hop wires are removed, or one or more internal connections are added to said one or more internal connections, or one or more internal hop wires are added to said one or more internal hop wires, or one or more external hop wires are added to said one or more external hop wires.
 15. The method of claim 9, wherein said plurality of computational blocks comprise either LUTs or memory or DSP processing block.
 16. The method of claim 9, wherein said semiconductor integrated circuit comprises a field programmable gate array.
 17. An article of manufacture, comprising: a computer readable non-transitory storage medium configured with instructions for generating a multi-stage pyramid network, said multi-stage pyramid network including connections to a plurality of computational blocks of a semiconductor integrated circuit arranged in a two-dimensional grid of a plurality of rows and a plurality of columns, said plurality of computational blocks comprising a plurality of inlet links and a plurality of outlet links; and said multi-stage pyramid network comprising a plurality of partial multi-stage pyramid networks and each partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks coupled to at least one of said plurality of computational blocks via said plurality of inlet links and said plurality of outlet links; and each partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks comprising one or more slices, each slice of said one or more slices comprising one or more rings, each ring of said one or more rings comprising a plurality of stages; and each stage of said plurality of stages comprising one or more switches of size d_(i)×d₀, where d_(i), d_(o) are integers, d_(i)≥2 and d_(o)≥2, each switch of said one or more switches of size d_(i)×d₀ having d_(i) incoming links and d₀ outgoing links, each switch of said one or more switches of size d_(i)×d₀ comprising a plurality of multiplexers of size d≥2, where d is an integer, with each multiplexer of said plurality of multiplexers comprising d inputs and one output; and wherein said at least one switch of size d_(i)×d₀ comprises one of a) a forward switch, b) both a forward switch and a U-turn switch, c) a forward switch, a backward switch and a U-turn switch, d) a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch e) a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree turn paths, f) an integrated switch of a forward switch, a backward switch and U-turn switch, g) an integrated switch of a forward switch, a backward switch and a U-turn switch without 180 degree turn paths h) an integrated switch of a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch and i) an integrated switch comprising a forward switch, a backward switch, a U-turn switch and a reverse U-turn switch without 180-degree turn paths; and wherein said d_(i) incoming links and said d_(o) outgoing links comprises one or more internal connections and one or more hop wires; and wherein each inlet link of said plurality of inlet links is connected to the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings of a first slice of said one or more slices of a first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks, and each outlet link of said plurality of outlet links is connected to a first input of said d inputs of one or more multiplexers of said plurality of multiplexers of one or more switches of said one or more switches of one or more stages of said plurality of stages of one or more rings of said one or more rings of one or more slices of said one or more slices of one or more partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks; and wherein a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said plurality of inlet links as a second partial multi-stage network of said plurality of partial multi-stage networks; and a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said plurality of outlet links as a second partial multi-stage network of said plurality of partial multi-stage networks; a first partial multi-stage network of said plurality of partial multi-stage networks comprises one of a) a same number and b) a different number of said one or more slices as a second partial multi-stage network of said plurality of partial multi-stage networks; a first slice of said one or more slices comprises one of a) a same number and b) a different number of said one or more rings as a second slice of said one or more slices; a first ring of said one or more rings comprises one of a) a same number and b) a different number of said plurality of stages as a second ring of said one or more rings; and a first stage of said plurality of stages comprises one of a) a same number and b) a different number of said one or more switches of size d_(i)×d₀ as a second stage of said plurality of stages; a first switch of said one or more switches of size d_(i)×d₀ is one of a) a same size and b) a different size as a second switch of said one or more switches of size d_(i)×d₀; and a first multiplexer in said plurality of multiplexers of size d≥2 is one of a) a same size and b) a different size as a second multiplexer in said plurality of multiplexers of size d≥2; and wherein each internal connection of said one or more internal connections connected from the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings to one of the d inputs of a second multiplexer of said plurality of multiplexers of a second switch of said one or more switches of a second stage of said plurality of stages of said first ring of said one or more rings; and said hop wires comprises one or more internal hop wires and one or more external hop wires; and wherein each internal hop wire of said one or more internal hop wires connected from the output of a first multiplexer of said plurality of multiplexers of a first switch of said one or more switches of a first stage of said plurality of stages of a first ring of said one or more rings of a first slice of said one or more slices of a first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks to one or more of the d inputs of one or more different multiplexers from said first multiplexer of said plurality of multiplexers of one or more different switches from said first switch of said one or more switches of one or more different stages from said first stage of said plurality of stages of one or more different rings from said first ring of said one or more rings of said first slice of said one or more slices of said first partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; and wherein each external hop wire of said one or more external hop wires connected from the output of a multiplexer of said plurality of multiplexers of a switch of said one or more switches of a stage of said plurality of stages of a ring of said one or more rings of a slice of said one or more slices of a first said partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks to one or more inputs of said d inputs of one or more multiplexers of said plurality of multiplexers of one or more switches of said one or more switches of said plurality of stages of one or more stages of said one or more rings of a slice of said one or more slices of one or more partial multi-stage pyramid networks different from first said partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; and wherein one or more external hop wires of said one or more external hop wires are one of a) connected between multiplexers of said plurality of multiplexers of switches of said one or more switches of same stages of said plurality of stages in two or more different partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks and b) connected between multiplexers of said plurality of multiplexers of switches of said one or more switches of in different stages said plurality of stages in two or more different partial multi-stage pyramid networks of said plurality of partial multi-stage pyramid networks, said instructions when executed by a computer causing said computer to perform operations including: setting up size of said one or more slices, setting up size of said one or more rings, setting up size of said plurality of stages, setting up size of said one or more switches, setting up size of said plurality of multiplexers, setting up number of inputs of each multiplexer of said plurality of multiplexers; setting up connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks; setting up connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings; selecting hop length of each external hop wire of said one or more external hop wires setting up connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks; setting up connections of said one or more internal hop wires between said one or more rings of the same slice of said one or more slices of a partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; setting up size of said plurality of rows and size of said plurality of columns in said two-dimensional grid; simulating said semiconductor integrated circuit with said plurality of rows and said plurality of columns of said plurality of partial multi-stage pyramid networks; routing one or more benchmarks on said semiconductor integrated circuit; checking if said one or more benchmarks are successfully routed; checking if all benchmarks of said one or more benchmarks are successfully routed, then computing a plurality of metrics including area, power, performance of benchmark and routing speed; checking if all benchmarks of said one or more benchmarks have met a criteria and saving said multi-stage pyramid network, or checking if said one or more benchmarks are not successfully routed, then changing either a) one or more of said size of said one or more slices, or b) said size of said one or more rings, or c) said size of said plurality of stages, or d) said size of said one or more switches, or e) said size of said plurality of multiplexers, or f) said number of inputs of each multiplexer of said plurality of multiplexers, or g) said connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks, or h) said hop length of each external hop wire of said one or more external hop wires, or i) said setting up of connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks, or j) said setting up of connections of said one or more internal hop wires between said one or more rings, or k) said setting up of connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings, or l) said size of said plurality of rows in said two-dimensional grid, or m) said size of said plurality of columns in said two-dimensional grid.
 18. The article of manufacture of claim 17, wherein said operations, Said setting up size of said one or more slices, said setting up size of said one or more rings, said setting up size of said plurality of stages, said setting up size of said one or more switches, said setting up size of said plurality of multiplexers, said setting up number of inputs of each multiplexer of said plurality of multiplexers; said setting up connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks; said setting up connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings; said selecting hop length of each external hop wire of said one or more external hop wires wherein size determines hop length, said setting up connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks; said setting up connections of said one or more internal hop wires between said one or more rings of the same slice of said one or more slices of a partial multi-stage pyramid network of said plurality of partial multi-stage pyramid networks; said setting up size of said plurality of rows and size of said plurality of columns in said two-dimensional grid; said simulating said semiconductor integrated circuit with said plurality of rows and said plurality of columns of said plurality of partial multi-stage pyramid networks; said routing one or more benchmarks on said semiconductor integrated circuit; said checking if said one or more benchmarks are successfully routed; said checking if all benchmarks of said one or more benchmarks are successfully routed, then computing a plurality of metrics including area, power, performance of benchmark and routing speed; said checking if all benchmarks of said one or more benchmarks have met a criteria and saving said multi-stage pyramid network, or said checking if said one or more benchmarks are not successfully routed, then changing either a) one or more of said size of said one or more slices, or b) said size of said one or more rings, or c) said size of said plurality of stages, or d) said size of said one or more switches, or e) said size of said plurality of multiplexers, or f) said number of inputs of each multiplexer of said plurality of multiplexers, or g) said connections of said plurality of inlet links and said plurality of outlet links to said plurality of partial multi-stage pyramid networks, or h) said hop length of each external hop wire of said one or more external hop wires, or i) said setting up of connections of said one or more external hop wires between said plurality of partial multi-stage pyramid networks, or j) said setting up of connections of said one or more internal hop wires between said one or more rings, or k) said setting up of connections of said one or more internal connections between said plurality of stages of said ring of said one or more rings, or l) said size of said plurality of rows in said two-dimensional grid, or m) said size of said plurality of columns in said two-dimensional grid, are repeated in a plurality of iterations, until said one or more benchmarks have met said criteria and then saving said multi-stage pyramid network or, one or more said operations are performed manually.
 19. The article of manufacture of claim 18, wherein in an iteration of said plurality of iterations, either one or more multiplexers of said plurality of multiplexers are removed including connections to its said inputs and said output or one or more multiplexers are added to said plurality of multiplexers including connections to its said inputs from one or more multiplexers of said plurality of multiplexers and connection to its said output to a first multiplexer of said plurality of multiplexers, or one or more internal connections of said one or more internal connections are removed, or one or more internal hop wires of said one or more internal hop wires are removed, or one or more external hop wires of said one or more external hop wires are removed, or one or more multiplexers are added to said plurality of multiplexers including connections to its said inputs and said output, or one or more internal connections are added to said one or more internal connections, or one or more internal hop wires are added to said one or more internal hop wires, or one or more external hop wires are added to said one or more external hop wires.
 20. The article of manufacture of claim 17, wherein said plurality of computational blocks comprise either LUTs or memory or DSP processing block, or said semiconductor integrated circuit comprises a field programmable gate array. 